DRA722_17 Datasheet, PDF (15/408 Pages) Texas Instruments – Infotainment Applications Processor

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BALL NUMBER
[1]
BALL NAME [2]
AD18
ddr1_a15
AF17
ddr1_ba0
AE18
ddr1_ba1
AB18
ddr1_ba2
AC18
ddr1_casn
AG24
ddr1_ck
AG22
ddr1_cke
AH23
ddr1_csn0
AB16
ddr1_csn1
AF25
ddr1_d0
AF26
ddr1_d1
AG26
ddr1_d2
AH26
ddr1_d3
AF24
ddr1_d4
AE24
ddr1_d5
AF23
ddr1_d6
AE23
ddr1_d7
AC23
ddr1_d8
AF27
ddr1_d9
AG27
ddr1_d10
AF28
ddr1_d11
AE26
ddr1_d12
AC25
ddr1_d13
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
SIGNAL NAME [3]
ddr1_a15
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_casn
ddr1_ck
ddr1_cke
ddr1_csn0
ddr1_csn1
ddr1_d0
ddr1_d1
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
Table 4-2. Ball Characteristics⁽¹⁾ (continued)
MUXMODE
[4]
TYPE [5]
0
O
0
O
0
O
0
O
0
O
0
O
0
O
0
O
0
O
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
BALL
RESET REL.
MUXMODE
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
PD
drive 1 (OFF)
1.35/1.5
vdds_ddr1 No
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1 No
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1 No
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1 No
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1 No
PD
drive 0 (OFF)
1.35/1.5
vdds_ddr1 No
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1 No
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1 No
PU
drive 1 (OFF)
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
PD
PD
1.35/1.5
vdds_ddr1 No
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
DSIS [14]
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Terminal Configuration and Functions
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