DRA722_17 Datasheet, PDF (177/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 6-1. OSC0 Crystal Electrical Characteristics (continued)
NAME
DESCRIPTION
ESR = 30 Ω
ESR = 40 Ω
19.2 MHz, 20 MHz, 27 MHz
19.2 MHz, 20 MHz
ESR = 50 Ω
27 MHz
C_O
Crystal shunt capacitance
19.2 MHz, 20 MHz
ESR = 60 Ω
27 MHz
19.2 MHz, 20 MHz
ESR = 80 Ω
27 MHz
19.2 MHz, 20 MHz
ESR = 100 Ω
27 MHz
L_M
Crystal motional inductance for f_p = 20 MHz
C_M
Crystal motional capacitance
Ethernet and MLB not used
t_j(xiosc0)
Frequency accuracy⁽¹⁾, xi_osc0
Ethernet RGMII and RMII
using derived clock
Ethernet MII using derived
clock
MLB using derived clock
(1) Crystal characteristics should account for tolerance+stability+aging.
MIN TYP MAX UNIT
7 pF
7 pF
5 pF
7 pF
Not Supported
-
5 pF
Not Supported
-
3 pF
Not Supported
-
10.16
mH
3.42
fF
±200
±50
ppm
±100
±50
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
Table 6-2 details the switching characteristics of the oscillator and the requirements of the input clock.
NAME
f_p
t_sX
Table 6-2. Oscillator Switching Characteristics—Crystal Mode
DESCRIPTION
Oscillation frequency
Start-up time
MIN
TYP
19.2, 20, 27 MHz
MAX
4
UNIT
MHz
ms
6.1.2.2 OSC0 Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_CLKIN1 clock input to the system. The external connections to support this are shown in Figure 6-4.
The xi_osc0 pin is connected to the 1.8-V LVCMOS-Compatible clock source. The xi_osc0 pin is left
unconnected. The vssa_osc0 pin is connected to board ground (VSS).
Device
xi_osc0
xo_osc0
vssa_osc0
NC
SPRS906_CLK_04
Figure 6-4. 1.8-V LVCMOS-Compatible Clock Input
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Clock Specifications 177