DRA722_17 Datasheet, PDF (237/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
gpmc_fclk
gpmc_clk
gpmc_csi
gpmc_a[27:1]
gpmc_ben0
gpmc_ben1
gpmc_advn_ale
gpmc_wen
gpmc_ad[15:0]
FA9
FA10
FA10
FA3
FA12
FA29
FA25
FA1
Valid Address
FA0
FA0
FA27
Data OUT
gpmc_waitj
DIR
OUT
GPMC_10
Figure 7-16. GPMC / NOR Flash - Asynchronous Write - Single Word Timing⁽¹⁾
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
Copyright © 2016–2017, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 237
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