DRA722_17 Datasheet, PDF (325/408 Pages) Texas Instruments – Infotainment Applications Processor

www.ti.com
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
NOTE
The general-purpose input/output i (i = 1 to 8) bank is also referred to as GPIOi.
7.27 Audio Tracking Logic (ATL)
The device contains four ATL modules that can be used for asynchronous sample rate conversion of
audio. The ATL calculates the error between two time bases, such as audio syncs, and optionally
generates an averaged clock using cycle stealing via software.
NOTE
For more detailed information on the ATL peripheral, see the Audio Tracking Logic (ATL)
chapter of the device-specific Technical Reference Manual.
NOTE
Audio Tracking Logic x (x= 1 to 4) module is also referred to as ATLx.
7.27.1 ATL Electrical Data/Timing
Table 7-139 and Figure 7-94 present switching characteristics for ATL
Table 7-139. Switching Characteristics Over Recommended Operating Conditions for ATL_CLKOUTx
NO. PARAMETER
DESCRIPTION
1 t_c(ATLCLKOUT)
2 t_{w(ATLCLKOUTL)}
3 t_{w(ATLCLKOUTH)}
Cycle time, ATL_CLKOUTx
Pulse Duration, ATL_CLKOUTx low
Pulse Duration, ATL_CLKOUTx high
(1) P = ATL_CLKOUTx period.
M = internal ATL PCLK period.
MIN
20
0.45*P - M⁽¹⁾
0.45*P - M⁽¹⁾
MAX
UNIT
ns
ns
ns
1
2
atl_clkx
3
SPRS906_TIMING_ATL_01
Figure 7-94. ATL_CLKOUTx Timing
7.28 System and Miscellaneous interfaces
The Device includes the following System and Miscellaneous interfaces:
• Sysboot Interface
• System DMA Interface
• Interrupt Controllers (INTC) Interface
• Observability Signal (OBS) Interface
7.29 Test Interfaces
The Device includes the following Test interfaces:
• IEEE 1149.1 Standard-Test-Access Port (JTAG)
• Trace Port Interface Unit (TPIU)
• Advanced Event Triggering Interface (AET)
Copyright © 2016–2017, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 325
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726