DRA722_17 Datasheet, PDF (220/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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BALL
A17
A20
C18
G16
D17
A21
AA3
AB3
AA4
AB9
B26
C23
BALL NAME
mcasp2_axr7
mcasp2_fsr
mcasp4_aclkx
mcasp4_axr0
mcasp4_axr1
mcasp4_fsx
mcasp5_aclkx
mcasp5_axr0
mcasp5_axr1
mcasp5_fsx
xref_clk2
xref_clk3
Table 7-20. Manual Functions Mapping for DSS VOUT2 IOSET2 (continued)
VOUT2_IOSET2_MANUAL1
A_DELAY (ps) G_DELAY (ps)
2492
0
VOUT2_IOSET2_MANUAL2
A_DELAY (ps) G_DELAY (ps)
354
483
2358
0
12
487
2524
0
1165
0
2578
0
797
0
2253
0
750
0
2478
0
823
0
4672
1737
3256
1798
4642
1286
3226
1347
4625
725
3209
786
4565
1062
3149
1123
0
49
1359
466
1947
0
36
0
VOUT2_IOSET2_MANUAL3
A_DELAY (ps) G_DELAY (ps)
845
0
513
0
1179
0
806
0
759
0
832
0
3226
1837
3196
1386
3179
825
3119
1162
1341
512
45
0
CFG REGISTER
CFG_MCASP2_AXR7_
OUT
CFG_MCASP2_FSR_O
UT
CFG_MCASP4_ACLKX_
OUT
CFG_MCASP4_AXR0_
OUT
CFG_MCASP4_AXR1_
OUT
CFG_MCASP4_FSX_O
UT
CFG_MCASP5_ACLKX_
OUT
CFG_MCASP5_AXR0_
OUT
CFG_MCASP5_AXR1_
OUT
CFG_MCASP5_FSX_O
UT
CFG_XREF_CLK2_OUT
CFG_XREF_CLK3_OUT
MUXMODE
6
vout2_d15
vout2_d9
vout2_d16
vout2_d18
vout2_d19
vout2_d17
vout2_d20
vout2_d22
vout2_d23
vout2_d21
vout2_clk
vout2_de
220 Timing Requirements and Switching Characteristics
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