DRA722_17 Datasheet, PDF (13/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
BALL NUMBER
[1]
BALL NAME [2]
K9
cap_vbbldo_dsp
Y14
cap_vbbldo_gpu
J10
cap_vbbldo_iva
J16
cap_vbbldo_mpu
T20
cap_vddram_core1
L9
cap_vddram_core3
J19
cap_vddram_core4
J9
cap_vddram_dsp
Y13
cap_vddram_gpu
K16
cap_vddram_iva
K19
cap_vddram_mpu
AE1
csi2_0_dx0
AF1
csi2_0_dx1
AF2
csi2_0_dx2
AH4
csi2_0_dx3
AH3
csi2_0_dx4
AD2
csi2_0_dy0
AE2
csi2_0_dy1
AF3
csi2_0_dy2
AG4
csi2_0_dy3
AG3
csi2_0_dy4
AG5
csi2_1_dx0
AG6
csi2_1_dx1
AH7
csi2_1_dx2
AH5
csi2_1_dy0
AH6
csi2_1_dy1
AG7
csi2_1_dy2
SIGNAL NAME [3]
cap_vbbldo_dsp
cap_vbbldo_gpu
cap_vbbldo_iva
cap_vbbldo_mpu
cap_vddram_core1
cap_vddram_core3
cap_vddram_core4
cap_vddram_dsp
cap_vddram_gpu
cap_vddram_iva
cap_vddram_mpu
csi2_0_dx0
csi2_0_dx1
csi2_0_dx2
csi2_0_dx3
csi2_0_dx4
csi2_0_dy0
csi2_0_dy1
csi2_0_dy2
csi2_0_dy3
csi2_0_dy4
csi2_1_dx0
csi2_1_dx1
csi2_1_dx2
csi2_1_dy0
csi2_1_dy1
csi2_1_dy2
Table 4-2. Ball Characteristics⁽¹⁾
MUXMODE
[4]
TYPE [5]
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
BALL
RESET REL.
MUXMODE
[8]
I/O
VOLTAGE
VALUE [9]
POWER [10]
HYS [11]
BUFFER
TYPE [12]
PULL
UP/DOWN
TYPE [13]
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
1.8
vdda_csi Yes
LVCMOS PU/PD
CSI2
DSIS [14]
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Terminal Configuration and Functions
13