DRA722_17 Datasheet, PDF (185/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
6.2.1 DPLL Characteristics
The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated
the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass
mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when
selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next
paragraph.
The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and
CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are
generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,
CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with
the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through
an asynchronous multplexing.
For more information, see the Power Reset Controller Management chapter of the Device TRM.
Table 6-12 summarizes DPLL type described in Section 6.2, DPLLs, DLLs Specifications introduction.
Table 6-12. DPLL Control Type
DPLL NAME
DPLL_ABE
DPLL_CORE
DPLL_DEBUGSS
DPLL_DSP
DPLL_GMAC
DPLL_HDMI
DPLL_IVA
DPLL_MPU
DPLL_PER
APLL_PCIE
DPLL_PCIE_REF
DPLL_SATA
DPLL_USB
DPLL_USB_OTG_SS
DPLL_VIDEO1
DPLL_DDR
DPLL_GPU
(1) DPLL is in the always-on domain.
(2) DPLL is not controlled by the PRCM.
TYPE
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-14 (Type B)
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-14 (Type B)
Table 6-14 (Type B)
Table 6-14 (Type B)
Table 6-14 (Type B)
Table 6-13 (Type A)
Table 6-13 (Type A)
Table 6-13 (Type A)
CONTROLLED BY PRCM
Yes⁽¹⁾
Yes⁽¹⁾
No⁽²⁾
Yes⁽¹⁾
Yes⁽¹⁾
No⁽²⁾
Yes⁽¹⁾
Yes⁽¹⁾
Yes⁽¹⁾
Yes⁽¹⁾
Yes⁽¹⁾
No⁽²⁾
Yes⁽¹⁾
No⁽²⁾
No⁽²⁾
Yes⁽¹⁾
Yes⁽¹⁾
Table 6-13 and Table 6-14 summarize the DPLL characteristics and assume testing over recommended
operating conditions.
NAME
f_input
f_internal
f_CLKINPHIF
f_CLKINPULOW
f_CLKOUT
Table 6-13. DPLL Type A Characteristics
DESCRIPTION
CLKINP input frequency
Internal reference frequency
CLKINPHIF input frequency
MIN
TYP
0.032
0.15
10
MAX
52
52
1400
UNIT
MHz
MHz
MHz
CLKINPULOW input frequency
0.001
600 MHz
CLKOUT output frequency
20⁽¹⁾
1400⁽²⁾ MHz
COMMENTS
F_INP
REFCLK
F_INPHIF
Bypass mode: f_CLKOUT =
f_CLKINPULOW / (M1 + 1) if
ulowclken = 1⁽⁶⁾
[M / (N + 1)] × F_INP × [1 / M2]
(in locked condition)
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Clock Specifications 185