DRA722_17 Datasheet, PDF (158/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 5-15. LVCMOS CSI2 DC Electrical Characteristics (continued)
PARAMETER
MIN
NOM
MAX
UNIT
V_HYS
Input hysteresis
25
mV
MIPI D-PHY Mode Ultralow Power Receiver (ULP-RX)
V_IH
Input high-level voltage
V_IL
Input low-level voltage
V_ITH
Input high-level threshold
V_ITL
Input low-level threshold
V_HYS
Input hysteresis
MIPI D-PHY Mode High-Speed Receiver (HS-RX)
880
mV
300
mV
880
mV
300
mV
25
mV
V_IDTH
V_IDTL
V_IDMAX
V_IHHS
V_ILHS
V_CMRXDC
Z_ID
Differential input high-level threshold
Differential input low-level threshold
Maximum differential input voltage
Single-ended input high voltage
Single-ended input low voltage
Differential input common-mode voltage
Differential input impedance
70
mV
–70
mV
270
mV
460
mV
–40
mV
70
330
mV
80
100
125
Ω
(1) V_ITH is the voltage at which the receiver is required to detect a high state in the input signal.
(2) V_ITL is the voltage at which the receiver is required to detect a low state in the input signal. V_ITL is larger than the maximum single-ended
line high voltage during HS transmission. Therefore, both low-power (LP) receivers will detect low during HS signaling.
(3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, V_HYST. V_HYST is the difference
between the V_ITH threshold and the V_ITL threshold.
(4) V_ITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during
ultralow power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state.
(5) Excluding possible additional RF interference of 200 mV_PP beyond 450 MHz.
(6) This value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and
variations below 450 MHz.
(7) This number corresponds to the VOD_MAX transmitter.
(8) Common mode is defined as the average voltage level of X and Y: V_CMRX = (V_X + V_Y) / 2.
(9) Common mode ripple may be due to t_R or t_F and transmission line impairments in the PCB.
(10) For more information regarding the pin name (or ball name) and corresponding signal name, see Table 4-7 CSI 2 Signal Descriptions.
5.7.8 BMLB18 Buffers DC Electrical Characteristics
Table 5-16 summarizes the DC electrical characteristics for BMLB18 Buffers.
Table 5-16. BMLB18 Buffers DC Electrical Characteristics
PARAMETER
MIN
NOM
Signal Names in MUXMODE 0: mlbp_dat_n / mlbp_dat_p / mlbp_sig_n / mlbp_sig_p / mlbp_clk_n / mlbp_clk_p;
Balls: AA2 / AA1 / AC2 / AC1 / AB2 / AB1;
1.8-V Mode
V_IH/V_IL
Input high-level threshold
VCM ±
50mV
V_HYS
V_OD
Input hysteresis voltage
Differential output voltage (measured with 50ohm resistor
between PAD and PADN)
NONE
300
V_CM
Common mode output voltage
1
C_PAD
Pad capacitance (including package capacitance)
MAX UNIT
V
mV
500 mV
1.5
V
4
pF
158 Specifications
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726