DRA722_17 Datasheet, PDF (135/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Instance Name
DMA_CRYPTO
DMM
DPLL_DEBUG
DSP1
DSS
DSS DISPC
Table 5-9. Maximum Supported Frequency (continued)
Module
Input Clock Name
DMA_CRYPTO_FC
LK
DMA_CRYPTO_IC
LK
DMM_CLK
SYSCLK
DSP1_FICLK
DSS_HDMI_CEC_
CLK
DSS_HDMI_PHY_
CLK
DSS_CLK
HDMI_CLKINP
DSS_L3_ICLK
VIDEO1_CLKINP
VIDEO2_CLKINP
DPLL_DSI1_A_CL
K1
DPLL_DSI1_B_CL
K1
DPLL_DSI1_C_CL
K1
DPLL_HDMI_CLK1
LCD1_CLK
LCD2_CLK
LCD3_CLK
F_CLK
Clock
Type
Int &
Func
Int
Int
Int
Int &
Func
Func
Func
Func
Func
Int
Func
Func
Func
Func
Func
Func
Func
Func
Func
Func
Max. Clock
Allowed (MHz)
266
133
266
38.4
DSP_CLK
0.032
48
192
38.4
266
38.4
38.4
209.3
209.3
209.3
185.6
209.3
209.3
209.3
209.3
PRCM Clock Name
L4SEC_L3_GICLK
L4SEC_L4_GICLK
EMIF_L3_GICLK
EMU_SYS_CLK
DSP1_GFCLK
HDMI_CEC_GFCLK
HDMI_PHY_GFCLK
DSS_GFCLK
HDMI_DPLL_CLK
DSS_L3_GICLK
VIDEO1_DPLL_CLK
VIDEO2_DPLL_CLK
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Clock Sources
PLL / OSC /
Source Clock
Name
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
SYS_CLK1
DSP_GFCLK
SYS_CLK1/610
FUNC_192M_CLK
DSS_CLK
SYS_CLK1
SYS_CLK2
CORE_X2_CLK
SYS_CLK1
SYS_CLK2
SYS_CLK1
SYS_CLK2
HDMI_CLK
VIDEO1_CLKOUT1
VIDEO1_CLKOUT3
HDMI_CLK
DPLL_ABE_X2_CL
K
HDMI_CLK
VIDEO1_CLKOUT3
HDMI_CLK
DPLL_DSI1_A_CL
K1
DSS_CLK
DPLL_DSI1_B_CL
K1
DSS_CLK
DPLL_DSI1_C_CL
K1
DSS_CLK
DPLL_DSI1_A_CL
K1
DPLL_DSI1_B_CL
K1
DPLL_DSI1_C_CL
K1
DSS_CLK
DPLL_HDMI_CLK1
PLL / OSC /
Source Name
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC1
DPLL_DSP
OSC1
DPLL_PER
DPLL_PER
OSC1
OSC2
DPLL_CORE
OSC1
OSC2
OSC1
OSC2
DPLL_HDMI
DPLL_VIDEO1
DPLL_VIDEO1
DPLL_HDMI
DPLL_ABE
DPLL_HDMI
DPLL_VIDEO1
DPLL_HDMI
See DSS data in
the rows above
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Specifications 135