DRA722_17 Datasheet, PDF (3/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
1.4 Functional Block Diagram
Figure 1-1 is functional block diagram for the device.
DRA72x
MPU
(1x ARM
Cortex–A15)
IVA HD
1080p Video
Co-Processor
GPU
(1x SGX544 3D)
BB2D
(GC320 2D)
DSP
(1x C66x
Co-Processor)
IPU1
(Dual Cortex–M4)
IPU2
(Dual Cortex–M4)
CAL
CSI2 x2
Radio Accelerators
VCP x2
HD ATL
Display Subsystem
1x GFX Pipeline
3x Video Pipeline
Blend / Scale
LCD1
LCD2
LCD3
HDMI 1.4a
EDMA
sDMA
MMU x2
VIP x1
VPE
High-Speed Interconnect
Spinlock
Mailbox x13
GPIO x8
System
Timers x16
WDT
RTC SS
KBD
PWM SS x3
HDQ
Connectivity
1x USB 3.0
Dual Mode FS/HS/SS
w/ PHY
2x USB 2.0
Dual Mode FS/HS
1x PHY, 1x ULPI
PCIe SS x2
MediaLB
MOST150
GMAC AVB
Serial Interfaces
UART x10
QSPI
McSPI x4 McASP x8
DCAN x2
I2C x6
Program/Data Storage
512-KB
RAM with ECC
GPMC / ELM
(NAND/NOR/
Async)
EMIF x1
1x 32-bit
DDR3/3L
256-KB ROM
MMC / SD x4
OCMC
SATA
DMM
intro-001
Copyright © 2016, Texas Instruments Incorporated
Figure 1-1. DRA72x Block Diagram
Copyright © 2016–2017, Texas Instruments Incorporated
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