DRA722_17 Datasheet, PDF (321/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
mmcj_clk
mmcj_cmd
mmcj_dat[i:0]
SDR122
SDR121
SDR120
SDR123
SDR124
Figure 7-89. MMC/SD/SDIOj in - SDR12 - Transmitter Mode
SPRS906_TIMING_MMC3_12
7.25.3.4 MMC3 and MMC4, SD SDR25 Mode
Figure 7-90, Figure 7-91, and Table 7-132, through Table 7-135 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD and SDIO SDR25 in receiver and transmitter mode.
Table 7-132. Timing Requirements for MMC3 - SDR25 Mode ⁽¹⁾
NO. PARAMETER
SDR253
SDR254
SDR257
SDR258
t_{su(cmdV-clkH)}
t_h(clkH-cmdV)
t_su(dV-clkH)
t_h(clkH-dV)
(1) i in [i:0] = 7
DESCRIPTION
MIN
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
5.3
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
1.6
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
5.3
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
1.6
MAX
UNIT
ns
ns
ns
ns
Table 7-133. Switching Characteristics for MMC3 - SDR25 Mode ⁽²⁾
NO. PARAMETER
SDR251 fop(clk)
SDR252 t_w(clkH)
H
SDR252L t_w(clkL)
DESCRIPTION
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
Pulse duration, mmc3_clk low
SDR255 t_d(clkL-cmdV)
SDR256 t_d(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
MIN
0.5*P-
0.270 ⁽¹⁾
0.5*P-
0.270 ⁽¹⁾
-8.8
-8.8
MAX
48
6.6
6.6
UNIT
MHz
ns
ns
ns
ns
Table 7-134. Timing Requirements for MMC4 - SDR25 Mode ⁽¹⁾
NO. PARAMETER
SDR255 t_{su(cmdV-clkH)}
SDR256 t_h(clkH-cmdV)
SDR257 t_su(dV-clkH)
SDR258 t_h(clkH-dV)
(1) i in [i:0] = 3
DESCRIPTION
MIN
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
5.3
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
1.6
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
5.3
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
1.6
MAX
UNIT
ns
ns
ns
ns
Table 7-135. Switching Characteristics for MMC4 - SDR25 Mode ⁽²⁾
NO. PARAMETER
SDR251 fop(clk)
SDR252 t_w(clkH)
H
DESCRIPTION
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
MIN
0.5*P-
0.270 ⁽¹⁾
MAX
48
UNIT
MHz
ns
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Timing Requirements and Switching Characteristics 321
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