DRA722_17 Datasheet, PDF (311/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 7-112. Switching Characteristics for MMC2 - JC64 Standard SDR Mode
NO. PARAMETER
SSDR1 fop(clk)
SSDR2H t_w(clkH)
DESCRIPTION
Operating frequency, mmc2_clk
Pulse duration, mmc2_clk high
SSDR2L t_w(clkL)
Pulse duration, mmc2_clk low
SSDR3 t_d(clkL-cmdV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
SSDR4 t_d(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
(1) P = output mmc2_clk period in ns
MIN
0.5*P-
0.172 (1)
0.5*P-
0.172 (1)
-16.96
-16.96
MAX
24
16.96
16.96
UNIT
MHz
ns
ns
ns
ns
SSDR2
SSDR2
SSDR1
mmc2_clk
SSDR6
SSDR5
mmc2_cmd
SSDR8
SSDR7
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_01
Figure 7-77. MMC/SD/SDIO in - Standard JC64 - Receiver Mode
SSDR2
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
SSDR2
SSDR1
SSDR3
SSDR4
Figure 7-78. MMC/SD/SDIO in - Standard JC64 - Transmitter Mode
SPRS906_TIMING_MMC2_02
7.25.2.2 High-speed JC64 SDR, 8-bit data, half cycle
Table 7-113 and Table 7-114 present Timing requirements and Switching characteristics for MMC2 - High
speed SDR in receiver and transmitter mode (see Figure 7-79 and Figure 7-80).
Table 7-113. Timing Requirements for MMC2 - JC64 High Speed SDR Mode
NO.
JC643
JC644
JC647
JC648
PARAMETER
t_{su(cmdV-clkH)}
t_h(clkH-cmdV)
t_su(dV-clkH)
t_h(clkH-dV)
DESCRIPTION
MIN
MAX
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge
5.6
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge
2.6
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge
5.6
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge
2.6
UNIT
ns
ns
ns
ns
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Timing Requirements and Switching Characteristics 311
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