DRA722_17 Datasheet, PDF (302/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
DSSD2
DSSD1
DSSD0
DSSD3
DSSD4
Figure 7-64. MMC/SD/SDIO in - Default Speed - Transmitter Mode
SPRS906_TIMING_MMC1_02
7.25.1.2 High speed, 4-bit data, SDR, half-cycle
Table 7-98 and Table 7-99 present Timing requirements and Switching characteristics for MMC1 - High
Speed in receiver and transmitter mode (see Figure 7-65 and Figure 7-66).
Table 7-98. Timing Requirements for MMC1 - SD Card High Speed
NO.
HSSD3
HSSD4
HSSD7
HSSD8
PARAMETER
t_{su(cmdV-clkH)}
t_h(clkH-cmdV)
t_su(dV-clkH)
t_h(clkH-dV)
DESCRIPTION
MIN
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
5.3
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
2.6
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
5.3
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
2.6
MAX
UNIT
ns
ns
ns
ns
Table 7-99. Switching Characteristics for MMC1 - SD Card High Speed
NO. PARAMETER
HSSD1 fop(clk)
HSSD2H t_w(clkH)
DESCRIPTION
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
HSSD2L t_w(clkL)
Pulse duration, mmc1_clk low
HSSD5 t_d(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
HSSD6 t_d(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
(1) P = output mmc1_clk period in ns
MIN
0.5*P-
0.185 ⁽¹⁾
0.5*P-
0.185 ⁽¹⁾
-7.6
-7.6
MAX
48
3.6
3.6
UNIT
MHz
ns
ns
ns
ns
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
HSSD1
HSSD2L
HSSD3
HSSD7
HSSD2H
HSSD4
HSSD8
Figure 7-65. MMC/SD/SDIO in - High Speed - Receiver Mode
SPRS906_TIMING_MMC1_03
302 Timing Requirements and Switching Characteristics
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