DRA722_17 Datasheet, PDF (322/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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Table 7-135. Switching Characteristics for MMC4 - SDR25 Mode ⁽²⁾ (continued)
NO. PARAMETER
SDR252L t_w(clkL)
DESCRIPTION
Pulse duration, mmc4_clk low
SDR255 t_d(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
SDR256 t_d(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
MIN
0.5*P-
0.270 ⁽¹⁾
-8.8
-8.8
MAX
6.6
6.6
UNIT
ns
ns
ns
mmcj_clk
mmcj_cmd
mmcj_dat[i:0]
SDR251
SDR252L
SDR253
SDR257
SDR252H
SDR254
SDR258
Figure 7-90. MMC/SD/SDIOj in - SDR25 - Receiver Mode
SPRS906_TIMING_MMC3_13
mmcj_clk
mmcj_cmd
mmcj_dat[i:0]
SDR251
SDR252H
SDR252L
SDR255
SDR255
SDR256
SDR256
Figure 7-91. MMC/SD/SDIOj in - SDR25 - Transmitter Mode
SPRS906_TIMING_MMC3_14
7.25.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
Figure 7-92, Figure 7-93, Table 7-136, and Table 7-137 present Timing requirements and Switching
characteristics for MMC3 - SDIO High speed SDR50 in receiver and transmitter mode.
Table 7-136. Timing Requirements for MMC3 - SDR50 Mode ⁽¹⁾
NO. PARAMETER
SDR503 t_{su(cmdV-clkH)}
SDR504 t_h(clkH-cmdV)
SDR507 t_su(dV-clkH)
SDR508 t_h(clkH-dV)
(1) i in [i:0] = 7
DESCRIPTION
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
MIN
1.48
1.6
1.48
1.6
MAX
UNIT
ns
ns
ns
ns
Table 7-137. Switching Characteristics for MMC3 - SDR50 Mode ⁽²⁾
NO. PARAMETER
SDR501 fop(clk)
SDR502 t_w(clkH)
H
SDR502L t_w(clkL)
DESCRIPTION
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
Pulse duration, mmc3_clk low
MIN
0.5*P-
0.270 ⁽¹⁾
0.5*P-
0.270 ⁽¹⁾
MAX
64
UNIT
MHz
ns
ns
322 Timing Requirements and Switching Characteristics
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