DRA722_17 Datasheet, PDF (257/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 7-41. Timing Requirements for SPI - Slave Mode (continued)
NO.
SS8 ⁽¹⁾
SS9 ⁽¹⁾
PARAMETER
t_{su(CS-SPICLK)}
t_h(SPICLK-CS)
DESCRIPTION
Setup time, spi_cs[x] valid before spi_sclk first edge
Hold time, spi_cs[x] valid after spi_sclk last edge
MODE
MIN
5
SPI1/2
5
SPI3
7.5
MAX
UNIT
ns
ns
ns
SPI4
6
ns
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz)
(3) 62.5ns Cycle time = 16 MHz
(4) P = SPICLK period.
(5) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
PHA=0
EPOL=1
spim_cs(IN)
SS2
SS1
SS8
SS3
SS9
spim_sclk(IN) ^POL=0
SS2
SS1
POL=1
SS3
spim_sclk(IN)
spim_d(OUT)
spim_cs(IN)
PHA=1
EPOL=1
spim_sclk(IN) ^POL=0
spim_sclk(IN)
POL=1
SS7
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
Bit n-4
SS2
SS1
SS8
SS3
SS3
SS1
SS2
Bit 0
SS9
spim_d(OUT)
SS6
Bit n-1
SS6
Bit n-2
SS6
SS6
Bit n-3
Bit 1
Figure 7-35. McSPI - Slave Mode Transmit
Bit 0
SPRS906_TIMING_McSPI_03
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Timing Requirements and Switching Characteristics 257
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