DRA722_17 Datasheet, PDF (376/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Device
rtc_osc_xi_clkin32
rtc_osc_xo
Crystal
Rd
(Optional)
C_f1
C_f2
www.ti.com
SPRS906_PCB_CLK_OSC_02
Figure 8-38. Grounding Scheme for Low-Frequency Clock
Figure 8-39 shows the grounding scheme for high-frequency clock.
Device
xi_oscj
xo_oscj
vssa_oscj
Crystal
Rd
(Optional)
C_f1
C_f2
(1) j in *_osc = 0 or 1
SPRS906_PCB_CLK_OSC_03
Figure 8-39. Grounding Scheme for High-Frequency Clock
8.7 DDR3 Board Design and Layout Guidelines
8.7.1 DDR3 General Board Layout Guidelines
To help ensure good signaling performance, consider the following board design guidelines:
• Avoid crossing splits in the power plane.
• Minimize Vref noise.
• Use the widest trace that is practical between decoupling capacitors and memory module.
• Maintain a single reference.
• Minimize ISI by keeping impedances matched.
• Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.
• Use proper low-pass filtering on the Vref pins.
• Keep the stub length as short as possible.
• Add additional spacing for on-clock and strobe nets to eliminate crosstalk.
• Maintain a common ground reference for all bypass and decoupling capacitors.
376 Applications, Implementation, and Layout
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