DRA722_17 Datasheet, PDF (190/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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V_ref = V_IH MIN (or V_OH MIN)
V_ref = V_IL MAX (or V_OL MAX)
pm_transvolt_prs403
Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels
7.3.1.2 1.8V and 3.3V Signal Transition Rates
The default SLEWCONTROL settings in each pad configuration register must be used to guaranteed
timings, unless specific instructions otherwise are given in the individual timing sub-sections of the
datasheet.
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
7.3.1.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routes. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information
specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to
attain accurate timing analysis for a given system, see the Using IBIS Models for timing Analysis
application report (literature number SPRA839). If needed, external logic hardware such as buffers may be
used to compensate any timing differences.
7.4 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between V_IH and V_IL (or between V_IL and V_IH) in a monotonic
manner. Monotonic transitions are more easily guaranteed with faster switching signals. Slower input
transitions are more susceptible to glitches due to noise and special care should be taken for slow input
clocks.
7.5 Virtual and Manual I/O Timing Modes
Some of the timings described in the following sections require the use of Virtual or Manual I/O Timing
Modes. Table 7-2 provides a summary of the Virtual and Manual I/O Timing Modes across all device
interfaces. The individual interface timing sections found later in this document provide the full description
of each applicable Virtual and Manual I/O Timing Mode. Refer to the "Pad Configuration" section of the
TRM for the procedure on implementing the Virtual and Manual Timing Modes in a system.
Virtual or Manual IO Mode Name
DPI Video Output
No Virtual or Manual IO Timing Mode Required
DSS_VIRTUAL1
VOUT1_MANUAL1
VOUT2_IOSET1_MANUAL1
VOUT2_IOSET1_MANUAL2
VOUT2_IOSET1_MANUAL3
VOUT2_IOSET2_MANUAL1
VOUT2_IOSET2_MANUAL2
VOUT2_IOSET2_MANUAL3
VOUT3_MANUAL1
GPMC
No Virtual or Manual IO Timing Mode Required
Table 7-2. Modes Summary
Data Manual Timing Mode
DPI1/3 Video Output Default Timings - Rising-edge Clock Reference
DPI1/3 Video Output Default Timings - Falling-edge Clock Reference
DPI1 Video Output Alternate Timings
DPI2 Video Output IOSET1 Alternate Timings
DPI2 Video Output IOSET1 Default Timings - Rising-edge Clock Reference
DPI2 Video Output IOSET1 Default Timings - Falling-edge Clock Reference
DPI2 Video Output IOSET2 Alternate Timings
DPI2 Video Output IOSET2 Default Timings - Rising-edge Clock Reference
DPI2 Video Output IOSET2 Default Timings - Falling-edge Clock Reference
DPI3 Video Output Alternate Timings
GPMC Asynchronous Mode Timings and Synchronous Mode - Default Timings
190 Timing Requirements and Switching Characteristics
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