DRA722_17 Datasheet, PDF (324/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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BALL
AC7
AC7
AC6
AC6
AC6
AC9
AC9
AC9
AC3
AC3
AC3
AC8
AC8
AC8
AD6
AD6
AD6
AB8
AB8
AB8
AB5
AB5
AB5
Table 7-138. Manual Functions Mapping for MMC3 (continued)
BALL NAME
mmc3_dat0
mmc3_dat0
mmc3_dat1
mmc3_dat1
mmc3_dat1
mmc3_dat2
mmc3_dat2
mmc3_dat2
mmc3_dat3
mmc3_dat3
mmc3_dat3
mmc3_dat4
mmc3_dat4
mmc3_dat4
mmc3_dat5
mmc3_dat5
mmc3_dat5
mmc3_dat6
mmc3_dat6
mmc3_dat6
mmc3_dat7
mmc3_dat7
mmc3_dat7
MMC3_MANUAL1
A_DELAY (ps)
G_DELAY (ps)
362
0
0
0
7
0
333
0
0
0
0
0
402
0
0
0
203
0
549
0
1
0
121
0
440
0
206
0
336
0
283
0
174
0
320
0
443
0
0
0
2
0
344
0
0
0
CFG REGISTER
CFG_MMC3_DAT0_OEN
CFG_MMC3_DAT0_OUT
CFG_MMC3_DAT1_IN
CFG_MMC3_DAT1_OEN
CFG_MMC3_DAT1_OUT
CFG_MMC3_DAT2_IN
CFG_MMC3_DAT2_OEN
CFG_MMC3_DAT2_OUT
CFG_MMC3_DAT3_IN
CFG_MMC3_DAT3_OEN
CFG_MMC3_DAT3_OUT
CFG_MMC3_DAT4_IN
CFG_MMC3_DAT4_OEN
CFG_MMC3_DAT4_OUT
CFG_MMC3_DAT5_IN
CFG_MMC3_DAT5_OEN
CFG_MMC3_DAT5_OUT
CFG_MMC3_DAT6_IN
CFG_MMC3_DAT6_OEN
CFG_MMC3_DAT6_OUT
CFG_MMC3_DAT7_IN
CFG_MMC3_DAT7_OEN
CFG_MMC3_DAT7_OUT
MUXMODE
0
mmc3_dat0
mmc3_dat0
mmc3_dat1
mmc3_dat1
mmc3_dat1
mmc3_dat2
mmc3_dat2
mmc3_dat2
mmc3_dat3
mmc3_dat3
mmc3_dat3
mmc3_dat4
mmc3_dat4
mmc3_dat4
mmc3_dat5
mmc3_dat5
mmc3_dat5
mmc3_dat6
mmc3_dat6
mmc3_dat6
mmc3_dat7
mmc3_dat7
mmc3_dat7
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-3 and described in Device TRM, Control
Module Chapter.
7.26 General-Purpose Interface (GPIO)
The general-purpose interface combines eight general-purpose input/output (GPIO) banks. Each GPIO
module provides up to 32 dedicated general-purpose pins with input and output capabilities; thus, the
general-purpose interface supports up to 215 pins.
These pins can be configured for the following applications:
• Data input (capture)/output (drive)
• Keyboard interface with a debounce cell
• Interrupt generation in active mode upon the detection of external events. Detected events are
processed by two parallel independent interrupt-generation submodules to support biprocessor
operations
• Wake-up request generation in idle mode upon the detection of external events
NOTE
For more information, see the General-Purpose Interface chapter of the Device TRM.
324 Timing Requirements and Switching Characteristics
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