 English |
|
|
|
|
|
|
|
| DRA722_17 Datasheet, PDF (251/408 Pages) Texas Instruments – Infotainment Applications Processor | |||
| |||
| ◁ |
www.ti.com
DRA722, DRA724, DRA725, DRA726
SPRS956B â MARCH 2016 â REVISED JANUARY 2017
HDQ
Command_byte_written
0_(LSB)
Break 1
6
tRSPS
7_(MSB)
Data_byte_received
1
0_(LSB)
6
Figure 7-28. HDQ Communication Timing
SPRS906_TIMING_HDQ1W_04
7.14.2 HDQ/1-Wire-1-Wire Mode
Table 7-36 and Table 7-37 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 7-29, Figure 7-30 and Figure 7-31).
Table 7-36. HDQ / 1-Wire Timing Requirements - 1-Wire Mode
NO.
PARAMETER
DESCRIPTION
10
tPDH
11
tPDL
12
tRDV
13
tREL
Presence pulse delay high
Presence pulse delay low
Read data valid time
Read data release time
MIN
15
60
tLOWR
0
MAX
60
240
15
45
UNIT
µs
µs
µs
µs
Table 7-37. HDQ / 1-Wire Switching Characteristics - 1-Wire Mode
NO.
PARAMETER
DESCRIPTION
MIN
14 tRSTL
Reset time low
480
15 tRSTH
Reset time high
480
16 tSLOT
Bit cycle time
60
17 tLOW1
Write bit-one time
1
18 tLOW0
Write bit-zero time(2)
60
19 tREC
Recovery time
1
20 tLOWR
Read bit strobe time(1)
1
(1) tLOWR (low pulse sent by the master) must be short as possible to maximize the master sampling window.
(2) tLOWR must be less than tSLOT.
1-WIRE
tRTSL
tPDH
tRSTH
tPDL
Figure 7-29. 1-Wire-Break (Reset)
MAX
960
120
15
120
15
UNIT
µs
µs
µs
µs
µs
µs
µs
SPRS906_TIMING_HDQ1W_05
1-WIRE
tLOWR
tRDV_and_tREL
tSLOT_and_tREC
Figure 7-30. 1-Wire-Read Bit (Data)
SPRS906_TIMING_HDQ1W_06
Copyright © 2016â2017, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 251
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese