DRA722_17 Datasheet, PDF (317/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 7-121. Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode ⁽²⁾ (continued)
NO.
DS2
PARAMETER
t_w(clkL)
DESCRIPTION
Pulse duration, mmc3_clk low
DS3
t_d(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
DS4 t_d(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
MIN
0.5*P-
0.270 ⁽¹⁾
-14.93
-14.93
MAX
14.93
14.93
UNIT
ns
ns
ns
Table 7-122. Timing Requirements for MMC4 - Default Speed Mode ⁽¹⁾
NO. PARAMETER
DS5
t_{su(cmdV-clkH)}
DS6
t_h(clkH-cmdV)
DS7 t_su(dV-clkH)
DS8 t_h(clkH-dV)
(1) i in [i:0] = 3
DESCRIPTION
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
MIN
5.11
20.46
5.11
20.46
MAX
UNIT
ns
ns
ns
ns
Table 7-123. Switching Characteristics for MMC4 - Default Speed Mode ⁽²⁾
NO.
DS0
DS1
PARAMETER
fop(clk)
t_w(clkH)
DESCRIPTION
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
DS2 t_w(clkL)
Pulse duration, mmc4_clk low
DS3
t_d(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
DS4 t_d(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
MIN
0.5*P-
0.270 ⁽¹⁾
0.5*P-
0.270 ⁽¹⁾
-14.93
-14.93
MAX
24
14.93
14.93
UNIT
MHz
ns
ns
ns
ns
DS2
DS1
DS0
mmcj_clk
DS6
mmcj_cmd
mmcj_dat[i:0]
DS5
DS8
DS7
SPRS906_TIMING_MMC3_07
Figure 7-84. MMC/SD/SDIOj in - Default Speed - Receiver Mode
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Timing Requirements and Switching Characteristics 317
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