DRA722_17 Datasheet, PDF (355/408 Pages) Texas Instruments – Infotainment Applications Processor

www.ti.com
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
• Number of vias on the differential pairs must be minimized, and identical on each line of the differential
pair. In case of multiple differential lanes in the same interface, all lines should have the same number
of vias.
• Shielded routing is to be promoted as much as possible (for instance, signals must be routed on
internal layers that are inside power and/or ground planes).
8.5.2 USB 2.0 Board Design and Layout Guidelines
This section discusses schematic guidelines when designing a universal serial bus (USB) system.
8.5.2.1 Background
Clock frequencies generate the main source of energy in a USB design. The USB differential DP/DM pairs
operate in high-speed mode at 480 Mbps. System clocks can operate at 12 MHz, 48 MHz, and 60 MHz.
The USB cable can behave as a monopole antenna; take care to prevent RF currents from coupling onto
the cable.
When designing a USB board, the signals of most interest are:
• Device interface signals: Clocks and other signal/data lines that run between devices on the PCB.
• Power going into and out of the cable: The USB connector socket pin 1 (VBUS ) may be heavily
filtered and need only pass low frequency signals of less than ~100 KHz. The USB socket pin 4
(analog ground) must be able to return the current during data transmission, and must be filtered
sparingly.
• Differential twisted pair signals going out on cable, DP and DM: Depending upon the data transfer rate,
these device terminals can have signals with fundamental frequencies of 240 MHz (high speed), 6
MHz (full speed), and 750 kHz (low speed).
• External crystal circuit (device terminals XI and X0): 12 MHz, 19.2 MHz, 24 MHz, and 48 MHz
fundamental. When using an external crystal as a reference clock, a 24 MHz and higher crystal is
highly recommended.
8.5.2.2 USB PHY Layout Guide
The following sections describe in detail the specific guidelines for USB PHY Layout.
8.5.2.2.1 General Routing and Placement
Use the following routing and placement guidelines when laying out a new design for the USB physical
layer (PHY). These guidelines help minimize signal quality and electromagnetic interference (EMI)
problems on a four-or-more layer evaluation module (EVM).
• Place the USB PHY and major components on the un-routed board first. For more details, see
Section 8.5.2.2.2.3.
• Route the high-speed clock and high-speed USB differential signals with minimum trace lengths.
• Route the high-speed USB signals on the plane closest to the ground plane, whenever possible.
• Route the high-speed USB signals using a minimum of vias and corners. This reduces signal
reflections and impedance changes.
• When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90°
turn. This reduces reflections on the signal traces by minimizing impedance discontinuities.
• Do not route USB traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or IC’s that use or duplicate clock signals.
• Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is
unavoidable, then the stub should be less than 200 mils.
• Route all high-speed USB signal traces over continuous planes (V_CC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
Copyright © 2016–2017, Texas Instruments Incorporated
Applications, Implementation, and Layout 355
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726