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DRA722_17 Datasheet, PDF (211/408 Pages) Texas Instruments – Infotainment Applications Processor
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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
7.7 Display Subsystem - Video Output Ports
Three Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 1, DPI
Video Output 2 and DPI Video Output 3.
NOTE
The DPI Video Output i (i = 1 to 3) interface is also referred to as VOUTi.
Every VOUT interface consists of:
• 24-bit data bus (data[23:0])
• Horizontal synchronization signal (HSYNC)
• Vertical synchronization signal (VSYNC)
• Data enable (DE)
• Field ID (FID)
• Pixel clock (CLK)
NOTE
For more information, see the Display Subsystem chapter of the Device TRM.
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in Table 7-16.
CAUTION
The I/O Timings provided in this section are valid only for some DSS usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
CAUTION
All pads/balls configured as vouti_* signals must be programmed to use slow
slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL]
register field to SLOW (0b1).
Table 7-14, Table 7-15 and Figure 7-6 assume testing over the recommended operating conditions and
electrical characteristic conditions.
Table 7-14. DPI Video Output i (i = 1..3) Default Switching Characteristics(1)(2)
NO.
PARAMETE
R
DESCRIPTION
D1 tc(clk)
Cycle time, output pixel clock vouti_clk
D2 tw(clkL)
D3 tw(clkH)
D5 td(clk-ctlV)
Pulse duration, output pixel clock vouti_clk low
Pulse duration, output pixel clock vouti_clk high
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
MODE
DPI1/2/3 in 1.8V mode
DPI2 in 3.3V mode
DPI1/3 in 3.3V mode
DPI1
MIN
11.76(3)
13.33(3)
P*0.5-1
P*0.5-1
-2.5
MAX
2.5
UNIT
ns
ns
ns
ns
ns
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Timing Requirements and Switching Characteristics 211
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