DRA722_17 Datasheet, PDF (143/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Instance Name
McASP7
McASP8
McSPI1
McSPI2
Table 5-9. Maximum Supported Frequency (continued)
Module
Input Clock Name
MCASP7_AHCLKX
MCASP7_FCLK
MCASP7_ICLK
MCASP8_AHCLKX
MCASP8_FCLK
MCASP8_ICLK
SPI1_ICLK
SPI1_FCLK
SPI2_ICLK
SPI2_FCLK
Clock
Type
Func
Func
Int
Func
Func
Int
Int
Func
Int
Func
Clock Sources
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
100
MCASP7_AHCLKX DPLL_ABE_X2_CL
K
SYS_CLK1
FUNC_96M_AON_
CLK
ATL_CLK3
ATL_CLK2
ATL_CLK1
ATL_CLK0
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
MLBP_CLK
192
MCASP7_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
266
L4PER2_L3_GICLK CORE_X2_CLK
100
MCASP8_AHCLKX DPLL_ABE_X2_CL
K
SYS_CLK1
FUNC_96M_AON_
CLK
ATL_CLK3
ATL_CLK2
ATL_CLK1
ATL_CLK0
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
MLBP_CLK
192
MCASP8_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
266
L4PER2_L3_GICLK CORE_X2_CLK
266
L4PER_L3_GICLK
CORE_X2_CLK
48
PER_48M_GFCLK PER_48M_GFCLK
266
L4PER_L3_GICLK
CORE_X2_CLK
48
PER_48M_GFCLK PER_48M_GFCLK
PLL / OSC /
Source Name
DPLL_ABE
OSC1
DPLL_PER
Module ATL
Module ATL
Module ATL
Module ATL
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_ABE
OSC1
DPLL_PER
Module ATL
Module ATL
Module ATL
Module ATL
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
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Specifications 143