DRA722_17 Datasheet, PDF (300/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 7-92. Switching Characteristics Over Recommended Operating Conditions for MLB 3-Pin Option
NO.
PARAMETER
DESCRIPTION
7
t_{d(MLBCLKH-MLBDATV)} Delay time, MLBCLKH rising to MLB_DAT/MLB_SIG valid
8
t_dis(MLBCLKL-
MLBDATZ)
Disable time, MLBCLKH falling to MLB_DAT/MLB_SIG Hi-Z
MODE
512FS
1024FS
512FS
1024FS
MIN MAX UNIT
0
10
ns
0
7
ns
0
14
ns
0
6.1
ns
Table 7-93 and Figure 7-62 present Timing Requirements for MLKCLK 6-Pin Option.
Table 7-93. Timing Requirements for MLBCLK 6-Pin Option ⁽¹⁾
NO.
PARAMETER
DESCRIPTION
MODE
MIN MAX UNIT
1
t_c(MLBCLKx)
2
t_w(MLBCLKx)
3
t_w(MLBCLKx)
Cycle time, MLB_CLKP/N
Pulse duration, MLB_CLKP/N high
Pulse duration, MLB_CLKP/N low
2048FS, 4096FS
10
ns
2048FS, 4096FS 4.5
ns
2048FS, 4096FS 4.5
ns
(1) The reference points for the rise and fall transitions are measured at 20%/80% of Vin+/-.
Table 7-94 and Table 7-95 present Timing Requirements and Switching Characteristics for MLB 6-Pin
Option.
Table 7-94. Timing Requirements for Receive Data for the MLB 6-Pin Option
NO.
5
PARAMETER
t_{su(DATx-CLKxH)}
DESCRIPTION
Setup time, MLBP_DATx/MLBP_SIGx input valid before
MLBP_CLKx rising
6
t_{h(CLKxH-DATx)}
Hold time, MLBP_DATx/MLBP_SIGx input valid after
MLBP_CLKx rising
(1) P= tc(MLBCLKx) period.
(2) n=0 or 1, corresponding to two captures per clock cycle.
MODE
2048FS
4096FS
2048FS
4096FS
MIN
1
0.5 -
n*P/2⁽¹⁾⁽²⁾
0.5
0.6 +
n*P/2⁽¹⁾⁽²⁾
MAX
UNIT
ns
ns
ns
ns
Table 7-95. Switching Characteristics Over Recommended Operating Conditions for MLB 6-Pin Option
NO.
7
PARAMETER
t_{d(CLKxH-DATxV)}
DESCRIPTION
Delay time, MLBPCLKxH rising to MLB_DATx/MLB_SIGx valid
8
t_{dis(CLKPH-DATPZ)}
Disable time, MLBPCLKxH rising to MLBP_DATx/MLBP_SIGx
Hi-Z
(1) P= tc(MLBCLKx) period.
(2) n=0 or 1, corresponding to two captures per clock cycle.
MODE
2048FS
4096FS
2048FS
4096FS
MIN
0.5
0.6 +
n*P/2⁽¹⁾⁽²⁾
0.5
0.6 +
n*P/2⁽¹⁾⁽²⁾
MAX
7
2.5 +
n*P/2
7
3.5 +
n*P/2
UNIT
ns
ns
ns
ns
7.25 eMMC/SD/SDIO
The Device includes the following external memory interfaces 4 MultiMedia Card/Secure Digital/Secure
Digital Input Output Interface (MMC/SD/SDIO)
NOTE
The eMMC/SD/SDIOi (i = 1 to 4) controller is also referred to as MMCi.
7.25.1 MMC1-SD Card Interface
MMC1 interface is compliant with the SD Standard v3.01 and it supports the following SD Card
applications:
300 Timing Requirements and Switching Characteristics
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