DRA722_17 Datasheet, PDF (216/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module Chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT1. See Table 7-2
Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 7-18
Manual Functions Mapping for DSS VOUT1 for a definition of the Manual modes.
Table 7-18 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
BALL
D11
F11
G10
D7
D8
A5
C6
C8
C7
B7
B8
A7
A8
F10
C9
A9
B9
A10
G11
E9
F9
F8
E7
E8
D9
B10
B11
C11
E11
Table 7-18. Manual Functions Mapping for DSS VOUT1
BALL NAME
vout1_clk
vout1_d0
vout1_d1
vout1_d10
vout1_d11
vout1_d12
vout1_d13
vout1_d14
vout1_d15
vout1_d16
vout1_d17
vout1_d18
vout1_d19
vout1_d2
vout1_d20
vout1_d21
vout1_d22
vout1_d23
vout1_d3
vout1_d4
vout1_d5
vout1_d6
vout1_d7
vout1_d8
vout1_d9
vout1_de
vout1_fld
vout1_hsync
vout1_vsync
VOUT1_MANUAL1
A_DELAY (ps)
G_DELAY (ps)
0
212
2502
0
2402
0
2147
0
2249
0
2410
0
2129
0
2279
0
2266
23
1798
0
2243
0
2127
0
2096
0
2375
0
2105
0
2120
0
2013
65
1887
0
2429
0
2639
0
2319
0
2227
0
2309
0
1999
0
2276
0
1933
0
1825
0
1741
13
2338
0
CFG REGISTER
CFG_VOUT1_CLK_OUT
CFG_VOUT1_D0_OUT
CFG_VOUT1_D1_OUT
CFG_VOUT1_D10_OUT
CFG_VOUT1_D11_OUT
CFG_VOUT1_D12_OUT
CFG_VOUT1_D13_OUT
CFG_VOUT1_D14_OUT
CFG_VOUT1_D15_OUT
CFG_VOUT1_D16_OUT
CFG_VOUT1_D17_OUT
CFG_VOUT1_D18_OUT
CFG_VOUT1_D19_OUT
CFG_VOUT1_D2_OUT
CFG_VOUT1_D20_OUT
CFG_VOUT1_D21_OUT
CFG_VOUT1_D22_OUT
CFG_VOUT1_D23_OUT
CFG_VOUT1_D3_OUT
CFG_VOUT1_D4_OUT
CFG_VOUT1_D5_OUT
CFG_VOUT1_D6_OUT
CFG_VOUT1_D7_OUT
CFG_VOUT1_D8_OUT
CFG_VOUT1_D9_OUT
CFG_VOUT1_DE_OUT
CFG_VOUT1_FLD_OUT
CFG_VOUT1_HSYNC_OUT
CFG_VOUT1_VSYNC_OUT
MUXMODE
0
vout1_clk
vout1_d0
vout1_d1
vout1_d10
vout1_d11
vout1_d12
vout1_d13
vout1_d14
vout1_d15
vout1_d16
vout1_d17
vout1_d18
vout1_d19
vout1_d2
vout1_d20
vout1_d21
vout1_d22
vout1_d23
vout1_d3
vout1_d4
vout1_d5
vout1_d6
vout1_d7
vout1_d8
vout1_d9
vout1_de
vout1_fld
vout1_hsync
vout1_vsync
216 Timing Requirements and Switching Characteristics
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726