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DRA722_17 Datasheet, PDF (157/408 Pages) Texas Instruments – Infotainment Applications Processor
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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
5.7.5 IHHV1833 Buffers DC Electrical Characteristics
Table 5-13 summarizes the DC electrical characteristics for IHHV1833 Buffers.
Table 5-13. IHHV1833 Buffers DC Electrical Characteristics
PARAMETER
Signal Names in MUXMODE 0: porz / rtc_porz / wakeup3 / wakeup0;
Balls: F22 / AB17 / AD17 / AC16;
1.8-V Mode
VIH
VIL
VHYS
IIN
CPAD
3.3-V Mode
Input high-level threshold
Input low-level threshold
Input hysteresis voltage
Input current at each I/O pin
Pad capacitance (including package capacitance)
VIH
VIL
VHYS
IIN
CPAD
Input high-level threshold
Input low-level threshold
Input hysteresis voltage
Input current at each I/O pin
Pad capacitance (including package capacitance)
MIN
NOM
1.2
40
0.02
1.2
40
5
5.7.6 LVCMOS OSC Buffers DC Electrical Characteristics
Table 5-14 summarizes the DC electrical characteristics for LVCMOS OSC Buffers.
MAX UNIT
V
0.4
V
mV
1
µA
1
pF
V
0.4
V
mV
8
µA
1
pF
Table 5-14. LVCMOS OSC Buffers DC Electrical Characteristics
PARAMETER
Signal Names in MUXMODE 0: rtc_osc_xi_clkin32 / rtc_osc_xo;
Balls: AE14 / AD14;
1.8-V Mode
VIH
Input high-level threshold
VIL
Input low-level threshold
MIN
NOM
0.65 *
VDDS
VHYS
Input hysteresis voltage
150
CPAD
Pad capacitance (including package capacitance)
MAX
0.35 *
VDDS
3
UNIT
V
V
mV
pF
5.7.7 LVCMOS CSI2 DC Electrical Characteristics
Table 5-15 summarizes the DC electrical characteristics for LVSMOS CSI2 Buffers.
Table 5-15. LVCMOS CSI2 DC Electrical Characteristics
PARAMETER
MIN
NOM
Signals MUXMODE0 : csi2_0_dx[4:0]; csi2_0_dy[4:0]; csi2_1_dx[2:0]; csi2_1_dy[2:0];
Bottom Balls: AE1 / AD2 / AF1 / AE2 / AF2 / AF3 / AH4 / AG4 / AH3 / AG3 / AG5 / AH5 / AG6 / AH6 / AH7 / AG7
MIPI D-PHY Mode Low-Power Receiver (LP-RX)
VIH
Input high-level voltage
880
VIL
Input low-level voltage
VITH
Input high-level threshold
VITL
Input low-level threshold
550
MAX
1350
550
880
UNIT
mV
mV
mV
mV
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Specifications 157