DRA722_17 Datasheet, PDF (285/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus
interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. Each PCIe
subsystem controller has support for PCIe Gen-II mode (5.0 Gbps /lane) and Gen-I mode (2.5 Gbps/lane)
(Single Lane and Flexible dual lane configuration).
The device PCIe supports the following features:
• 16-bit operation @250 MHz on PIPE interface (per 16-bit lane)
• Supports 2 ports x 1 lane or 1 port x 2 lanes configuration
• Single virtual channel (VC0), single traffic class (TC0)
• Single function in end-point mode
• Automatic width and speed negotiation
• Max payload: 128 byte outbound, 256 byte inbound
• Automatic credit management
• ECRC generation and checking
• Configurable BAR filtering
• Legacy interrupt reception (RC) and generation (EP)
• MSI generation and reception
• PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions)
• All PCI Device Power Management D-states with the exception of D3_cold / L2 state
The PCIe controller on this device conforms to the PCI Express Base 3.0 Specification, revision 1.0 and
the PCI Local Bus Specification, revision 3.0
NOTE
For more information, see the PCIe Controller section of the Device TRM.
7.22 Controller Area Network Interface (DCAN)
The device provides two DCAN interfaces for supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the following features:
• Supports CAN protocol version 2.0 part A, B
• Bit rates up to 1 MBit/s
• 64 message objects
• Individual identifier mask for each message object
• Programmable FIFO mode for message objects
• Programmable loop-back modes for self-test operation
• Suspend mode for debug support
• Software module reset
• Automatic bus on after Bus-Off state by a programmable 32-bit timer
• Direct access to Message RAM during test mode
• CAN Rx/Tx pins are configurable as general-purpose IO pins
• Two interrupt lines (plus additional parity-error interrupts line)
• RAM initialization
• DMA support
NOTE
For more information, see the DCAN section of the Device TRM.
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Timing Requirements and Switching Characteristics 285
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Product Folder Links: DRA722 DRA724 DRA725 DRA726