DRA722_17 Datasheet, PDF (306/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
SDR501
SDR502H
SDR502L
SDR505
SDR505
SDR506
SDR506
SPRS906_TIMING_MMC1_10
Figure 7-72. MMC/SD/SDIO in - High Speed SDR50 - Transmitter Mode
7.25.1.6 UHS-I SDR104, 4-bit data, half-cycle
Table 7-106 presents Timing requirements and Switching characteristics for MMC1 - SDR104 in receiver
and transmitter mode (see Figure 7-73 and Figure 7-74).
Table 7-106. Switching Characteristics for MMC1 - SD Card SDR104 Mode
NO. PARAMETER
DESCRIPTION
SDR1041 fop(clk)
Operating frequency, mmc1_clk
SDR1042 t_w(clkH)
H
Pulse duration, mmc1_clk high
SDR1042 t_w(clkL)
L
Pulse duration, mmc1_clk low
SDR1045 t_d(clkL-cmdV)
SDR1046 t_d(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
(1) P = output mmc1_clk period in ns
MIN
0.5*P-
0.185 ⁽¹⁾
0.5*P-
0.185 ⁽¹⁾
-1.09
-1.09
MAX
192
0.49
0.49
UNIT
MHz
ns
ns
ns
ns
SDR1041
SDR1042L
SDR1042H
mmc1_clk
SDR1043
SDR1044
mmc1_cmd
SDR1047
SDR1048
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_11
Figure 7-73. MMC/SD/SDIO in - High Speed SDR104 - Receiver Mode
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
SDR1041
SDR1042H
SDR1042L
SDR1045
SDR1045
SDR1046
SDR1046
SPRS906_TIMING_MMC1_12
Figure 7-74. MMC/SD/SDIO in - High Speed SDR104 - Transmitter Mode
7.25.1.7 UHS-I DDR50, 4-bit data
Table 7-107 and Table 7-108 present Timing requirements and Switching characteristics for MMC1 -
DDR50 in receiver and transmitter mode (see Figure 7-75 and Figure 7-76).
306 Timing Requirements and Switching Characteristics
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