DRA722_17 Datasheet, PDF (390/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
DDR Address and Control Input Buffers
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Processor
Address and Control
Output Buffer
Address and Control
Terminator
Rtt
A1
A2
A3
AT
Vtt
SPRS906_PCB_DDR3_13
Figure 8-52. ADDR_CTRL Topology for Two DDR3 Devices
8.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
Figure 8-53 shows the CK routing for two DDR3 devices placed on the same side of the PCB. Figure 8-54
shows the corresponding ADDR_CTRL routing.
DDR_1V5
A2
A3
A2
A3
=
Rcp
AT
AT
Rcp
Cac
0.1 µF
SPRS906_PCB_DDR3_14
Figure 8-53. CK Routing for Two Single-Side DDR3 Devices
390 Applications, Implementation, and Layout
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