DRA722_17 Datasheet, PDF (139/408 Pages) Texas Instruments – Infotainment Applications Processor

www.ti.com
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Instance Name
McASP1
Table 5-9. Maximum Supported Frequency (continued)
Module
Input Clock Name
MCASP1_AHCLKR
MCASP1_AHCLKX
MCASP1_FCLK
MCASP1_ICLK
Clock
Type
Func
Func
Func
Int
Clock Sources
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
100
MCASP1_AHCLKR DPLL_ABE_X2_CL
K
SYS_CLK1
FUNC_96M_AON_
CLK
ATLCLK0
ATLCLK1
ATLCLK2
ATLCLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
MLBP_CLK
100
MCASP1_AHCLKX DPLL_ABE_X2_CL
K
SYS_CLK1
FUNC_96M_AON_
CLK
ATLCLK0
ATLCLK1
ATLCLK2
ATLCLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
MLBP_CLK
192
MCASP1_AUX_GFCLK PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
266
IPU_L3_GICLK
CORE_X2_CLK
PLL / OSC /
Source Name
DPLL_ABE
OSC1
DPLL_PER
Module ATL
Module ATL
Module ATL
Module ATL
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
OSC1
DPLL_PER
Module ATL
Module ATL
Module ATL
Module ATL
OSC2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726
Specifications 139