DRA722_17 Datasheet, PDF (187/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 6-14. DPLL Type B Characteristics (continued)
NAME
DESCRIPTION
MIN
p_relock-L
Relock time—Phase lock⁽³⁾ (LP
relock time from bypass)
(1) The minimum frequency on CLKOUT is assuming M2 = 1.
TYP
MAX UNIT
9 + 125 ×
REFCLKs
µs
COMMENTS
For M2 > 1, the minimum frequency on this clock will further scale down by factor of M2.
(2) The maximum frequency on CLKOUT is assuming M2 = 1.
(3) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(4) Bypass mode: f_CLKOUT = F_INP if ULOWCLKEN = 0. For more information, see the Device TRM.
(5) For output clocks, there are two frequency ranges according to the SELFREQDCO setting. For more information, see the Device TRM.
6.2.2 DLL Characteristics
Table 6-15 summarizes the DLL characteristics and assumes testing over recommended operating
conditions.
NAME
f_input
t_lock
t_relock
Table 6-15. DLL Characteristics
DESCRIPTION
MIN
Input clock frequency (EMIF_DLL_FCLK)
Lock time
Relock time (a change of the DLL frequency implies that DLL must relock)
TYP
MAX
UNIT
266
MHz
50k
cycles
50k
cycles
6.2.3 DPLL and DLL Noise Isolation
NOTE
For more information on DPLL and DLL decoupling capacitor requirements, see the External
Capacitors / Voltage Decoupling Capacitors / I/O and Analog Voltage Decoupling / VDDA
Power Domain section.
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Clock Specifications 187