DRA722_17 Datasheet, PDF (289/408 Pages) Texas Instruments – Infotainment Applications Processor

www.ti.com
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
SIGNALS
mii1_txd3
mii1_txd2
mii1_txd1
mii1_txd0
mii1_rxd3
mii1_rxd2
mii1_rxd1
mii1_rxd0
mii1_col
mii1_rxer
mii1_txer
mii1_txen
mii1_crs
mii1_rxclk
mii1_txclk
mii1_rxdv
mii0_txd3
mii0_txd2
mii0_txd1
mii0_txd0
mii0_rxd3
mii0_rxd2
mii0_rxd1
mii0_rxd0
mii0_txclk
mii0_txer
mii0_rxer
mii0_rxdv
mii0_crs
mii0_col
mii0_rxclk
mii0_txen
Table 7-72. GMAC MII IOSETs
BALL
C5
D6
B2
C4
F5
E4
C1
E6
B4
B3
A3
A4
B5
D5
C3
C2
IOSET5
MUX
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
7.23.2 GMAC MDIO Interface Timings
BALL
IOSET6
MUX
V5
3
V4
3
Y2
3
W2
3
W9
3
V9
3
V6
3
U6
3
U5
3
U4
3
U7
3
V2
3
V7
3
V1
3
Y1
3
V3
3
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-73, Table 7-73 and Figure 7-57 present timing requirements for MDIO.
Copyright © 2016–2017, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 289
Submit Documentation Feedback
Product Folder Links: DRA722 DRA724 DRA725 DRA726