DRA722_17 Datasheet, PDF (209/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
BALL
J6
H4
H5
N6
M4
H6
BALL NAME
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_ben0
gpmc_ben1
gpmc_cs1
Table 7-12. Manual Functions Mapping for VIN1B (IOSET5) and VIN2B (IOSET9) (continued)
VIP_MANUAL10
A_DELAY (ps) G_DELAY (ps)
1426
1166
1362
1094
1283
809
1978
780
0
0
1411
982
VIP_MANUAL11
A_DELAY (ps) G_DELAY (ps)
1842
732
1797
584
1760
338
2327
389
0
0
1857
536
CFG REGISTER
CFG_GPMC_A25_IN
CFG_GPMC_A26_IN
CFG_GPMC_A27_IN
CFG_GPMC_BEN0_IN
CFG_GPMC_BEN1_IN
CFG_GPMC_CS1_IN
MUXMODE
4
6
-
vin2b_d6
-
vin2b_d7
-
vin2b_hsync1
-
vin2b_de1
vin2b_clk1
vin2b_fld1
vin2a_de0
vin2b_vsync1
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Table 7-13 Manual Functions Mapping for VIN1A (IOSET8/9/10) for a definition of the Manual modes.
Table 7-13 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL
AC5
AB4
C14
G12
F12
B13
A12
E14
A13
G14
F14
B12
A11
D14
A19
C15
A16
A18
BALL NAME
gpio6_10
gpio6_11
mcasp1_aclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
mcasp1_axr13
mcasp1_axr14
mcasp1_axr15
mcasp1_axr8
mcasp1_axr9
mcasp1_fsx
mcasp2_aclkx
mcasp2_axr2
mcasp2_axr3
mcasp2_fsx
Table 7-13. Manual Functions Mapping for VIN1A (IOSET8/9/10)
VIP_MANUAL15
A_DELAY (ps) G_DELAY (ps)
2131
2198
3720
2732
2447
0
3061
0
3113
0
2803
0
3292
0
2854
0
2813
0
2471
0
2815
0
2965
0
3082
0
2898
0
2413
0
2478
0
2806
0
2861
78
VIP_MANUAL16
A_DELAY (ps) G_DELAY (ps)
2170
2180
4106
2448
3042
0
3380
292
3396
304
3362
0
3357
546
3145
320
3229
196
3053
0
3225
201
3427
83
3253
440
3368
139
2972
0
3062
0
3175
242
2936
599
CFG REGISTER
CFG_GPIO6_10_IN
CFG_GPIO6_11_IN
CFG_MCASP1_ACLKX_IN
CFG_MCASP1_AXR0_IN
CFG_MCASP1_AXR1_IN
CFG_MCASP1_AXR10_IN
CFG_MCASP1_AXR11_IN
CFG_MCASP1_AXR12_IN
CFG_MCASP1_AXR13_IN
CFG_MCASP1_AXR14_IN
CFG_MCASP1_AXR15_IN
CFG_MCASP1_AXR8_IN
CFG_MCASP1_AXR9_IN
CFG_MCASP1_FSX_IN
CFG_MCASP2_ACLKX_IN
CFG_MCASP2_AXR2_IN
CFG_MCASP2_AXR3_IN
CFG_MCASP2_FSX_IN
MUXMODE
7
9
-
vin1a_clk0
-
vin1a_de0
vin1a_fld0
-
vin1a_vsync0
-
vin1a_hsync0
-
vin1a_d13
-
vin1a_d12
-
vin1a_d11
-
vin1a_d10
-
vin1a_d9
-
vin1a_d8
-
vin1a_d15
-
vin1a_d14
-
vin1a_de0
-
vin1a_d7
-
vin1a_d5
-
vin1a_d4
-
vin1a_d6
-
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Timing Requirements and Switching Characteristics 209