DRA722_17 Datasheet, PDF (259/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
SIGNALS
spi4_cs1
spi4_cs2
spi4_cs3
spi4_d0
spi4_d1
spi4_sclk
IOSET1
BALL
MUX
P4
8
R3
8
T2
8
N9
8
R4
8
N7
8
Table 7-42. McSPI3/4 IOSETs (continued)
IOSET2
BALL
MUX
P4
8
R3
8
T2
8
F2
8
G6
8
G1
8
IOSET3
BALL
MUX
Y1
8
W9
8
V9
8
V6
7
U7
7
V7
7
IOSET4
BALL
MUX
Y1
8
W9
8
V9
8
AB3
2
AB9
2
AA3
2
IOSET5
BALL
MUX
Y1
8
W9
8
V9
8
AB8
1
AD6
1
AC8
1
7.17 Quad Serial Peripheral Interface (QSPI)
The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to
external SPI devices. This module has a memory mapped register interface, which provides a direct
interface for accessing data from external SPI devices and thus simplifying software requirements. It
works as a master only. There is one QSPI module in the device and it is primary intended for fast
booting from quad-SPI flash memories.
General SPI features:
• Programmable clock divider
• Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)
• 4 external chip select signals
• Support for 3-, 4- or 6-pin SPI interface
• Programmable CS_N to DOUT delay from 0 to 3 DCLKs
• Programmable signal polarities
• Programmable active clock edge
• Software controllable interface allowing for any type of SPI transfer
NOTE
For more information, see the Quad Serial Peripheral Interface section of the Device TRM.
CAUTION
The I/O Timings provided in this section are only valid when all QSPI Chip
Selects used in a system are configured to use the same Clock Mode (either
Clock Mode 0 or Clock Mode 3).
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 7-43 and Table 7-44 Present Timing and Switching Characteristics for Quad SPI Interface.
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Timing Requirements and Switching Characteristics 259
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