DRA722_17 Datasheet, PDF (153/408 Pages) Texas Instruments – Infotainment Applications Processor

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5.6 Power Consumption Summary
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
NOTE
Maximum power consumption for this SoC depends on the specific use conditions for the
end system. Contact your TI representative for assistance in estimating maximum power
consumption for the end system use case.
5.7 Electrical Characteristics
NOTE
The data specified in Section 5.7.1 through Section 5.7.14 are subject to change.
NOTE
The interfaces or signals described in Section 5.7.1 through Section 5.7.14 correspond to the
interfaces or signals available in multiplexing mode 0 (Function 1).
All interfaces or signals multiplexed on the balls described in these tables have the same DC
electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which
case different DC electrical characteristics are specified for the different multiplexing modes
(Functions).
5.7.1 LVCMOS DDR DC Electrical Characteristics
Table 5-10 summarizes the DC electrical characteristics for LVCMOS DDR Buffers.
NOTE
For more information on the I/O cell configurations (i[2:0], sr[1:0]), see the Chapter Control
Module of the Device TRM.
Table 5-10. LVCMOS DDR DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0 (Single-Ended Signals): ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn[1:0],
ddr1_cke, ddr1_odt[1:0], ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst, ddr1_ecc_d[7:0], ddr1_dqm_ecc;
Balls: AH23 / AB16 / AG22 / AE20 / AC17 / AC18 / AF20 /AH21 / AG21 / AF17 / AE18 / AB18 / AD20 / AC19 / AC20 / AB19 / AF21 / AH22
/ AG23 / AE21 / AF22 / AE22 / AD21 / AD22 / AC21 / AF18 / AE17 / AD18 / AF25 / AF26 / AG26 / AH26 / AF24 / AE24 / AF23 / AE23 /
AC23 / AF27 / AG27 / AF28 / AE26 / AC25 / AC24 / AD25 / V20 / W20 / AB28 / AC28 / AC27 / Y19 / AB27 / Y20 / AA23 / Y22 / Y23 / AA24
/ Y24 / AA26 / AA25 / AA28 / W22 / V23 / W19 / W23 / Y25 / V24 / V25 / Y26 / AD23 / AB23 / AC26 / AA27 / V26;
Driver Mode
V_OH
V_OL
C_PAD
Z_O
High-level output threshold (I_OH = 0.1 mA)
Low-level output threshold (I_OL = 0.1 mA)
Pad capacitance (including package capacitance)
Output impedance (drive
strength)
l[2:0] = 000
(Imp80)
0.9*VDDS
V
0.1*VDDS
V
3
pF
80
Ω
l[2:0] = 001
60
(Imp60)
l[2:0] = 010
48
(Imp48)
l[2:0] = 011
40
(Imp40)
l[2:0] = 100
34
(Imp34)
Single-Ended Receiver Mode
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Specifications 153