DRA722_17 Datasheet, PDF (258/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
PHA=0
EPOL=1
spim_cs(IN)
SS2
SS1
SS8
SS3
SS9
spim_sclk(IN) ^POL=0
SS2
SS1
POL=1
SS3
spim_sclk(IN)
spim_d(IN)
spim_cs(IN)
PHA=1
EPOL=1
spim_sclk(IN) ^POL=0
spim_sclk(IN)
POL=1
SS5
SS4
Bit n-1
SS4
SS5
Bit n-2
Bit n-3
Bit n-4
Bit 0
SS2
SS1
SS8
SS3
SS9
SS3
SS1
SS2
spim_d(IN)
SS4
SS5
SS4
SS5
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit0
Figure 7-36. McSPI - Slave Mode Receive
SPRS906_TIMING_McSPI_04
In Table 7-42 are presented the specific groupings of signals (IOSET) for use with SPI3 and SPI4.
SIGNALS
IOSET1
BALL
MUX
spi3_cs0
D11
8
spi3_cs1
B11
8
spi3_cs2
F11
8
spi3_cs3
A10
8
spi3_d0
C11
8
spi3_d1
B10
8
spi3_sclk
E11
8
spi4_cs0
P9
8
Table 7-42. McSPI3/4 IOSETs
IOSET2
BALL
MUX
V9
7
AC3
1
W9
7
Y1
7
V2
7
F3
8
IOSET3
BALL
MUX
McSPI3
A12
3
E14
3
F11
8
A10
8
B13
3
A11
3
B12
3
McSPI4
U6
7
IOSET4
BALL
MUX
D17
2
B11
8
F11
8
A10
8
G16
2
A21
2
C18
2
AA4
2
IOSET5
BALL
MUX
AC9
1
AC3
1
AC6
1
AC7
1
AC4
1
AB5
1
258 Timing Requirements and Switching Characteristics
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