DRA722_17 Datasheet, PDF (134/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
(1) N/A in this table stands for Not Applicable.
(2) Maximum supported frequency is limited according to the Device Speed Grade (see Table 5-5).
5.5.3 Maximum Supported Frequency
Device modules either receive their clock directly from an external clock input, directly from a PLL, or from
a PRCM. Table 5-9 lists the clock source options for each module on this device, along with the maximum
frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers
must be programmed not to exceed the maximum frequencies listed in this table.
Instance Name
AES1
AES2
ATL
Table 5-9. Maximum Supported Frequency
Module
Input Clock Name
AES1_L3_CLK
AES2_L3_CLK
ATL_ICLK_L3
ATLPCLK
Clock
Type
Int
Int
Int
Func
Max. Clock
Allowed (MHz)
266
266
266
266
PRCM Clock Name
L4SEC_L3_GICLK
L4SEC_L3_GICLK
ATL_L3_GICLK
ATL_GFCLK
Clock Sources
PLL / OSC /
Source Clock
Name
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
PER_ABE_X1_GF
CLK
FUNC_32K_CLK
BB2D
COUNTER_32K
BB2D_FCLK
BB2D_ICLK
COUNTER_32K_F
CLK
COUNTER_32K_IC
LK
CTRL_MODULE_B L3INSTR_TS_GCL
ANDGAP
K
CTRL_MODULE_C L4CFG_L4_GICLK
ORE
CTRL_MODULE_ WKUPAON_GICLK
WKUP
DCAN1
DCAN1_FCLK
DCAN1_ICLK
DCAN2
DES3DES
DLL
DLL_AGING
DCAN2_FCLK
DCAN2_ICLK
DES_CLK_L3
EMIF_DLL_FCLK
FCLK
Func
Int
Func
Int
Int
Int
Int
Func
Int
Func
Int
Int
Func
Int
354.6
266
0.032
BB2D_GFCLK
DSS_L3_GICLK
FUNC_32K_CLK
HDMI_CLK
VIDEO1_CLK
BB2D_GFCLK
CORE_X2_CLK
SYS_CLK1/610
38.4
WKUPAON_GICLK
SYS_CLK1
DPLL_ABE_X2_CL
K
4.8
L3INSTR_TS_GCLK
SYS_CLK1
DPLL_ABE_X2_CL
K
133
L4CFG_L4_GICLK
CORE_X2_CLK
38.4
38.4
266
38.4
266
266
EMIF_DLL_FC
LK
38.4
WKUPAON_GICLK
DCAN1_SYS_CLK
WKUPAON_GICLK
DCAN2_SYS_CLK
L4PER2_L3_GICLK
L4SEC_L3_GICLK
EMIF_DLL_GCLK
L3INSTR_DLL_AGING
_GCLK
SYS_CLK1
DPLL_ABE_X2_CL
K
SYS_CLK1
SYS_CLK2
SYS_CLK1
DPLL_ABE_X2_CL
K
SYS_CLK1
CORE_X2_CLK
CORE_X2_CLK
EMIF_DLL_GCLK
SYS_CLK1
DPLL_ABE_X2_CL
K
PLL / OSC /
Source Name
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_ABE
OSC1
RTC Oscillator
DPLL_HDMI
DPLL_VIDEO1
DPLL_CORE
DPLL_CORE
OSC1
OSC1
DPLL_ABE
OSC1
DPLL_ABE
DPLL_CORE
OSC1
DPLL_ABE
OSC1
OSC2
OSC1
DPLL_ABE
OSC1
DPLL_CORE
DPLL_CORE
DPLL_DDR
OSC1
DPLL_ABE
134 Specifications
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