DRA722_17 Datasheet, PDF (268/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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Table 7-51. Switching Characteristics Over Recommended Operating Conditions for
McASP3/4/5/6/7/8⁽¹⁾ (continued)
NO. PARAMETER DESCRIPTION
MODE
MIN
13
t_{d(ACLK-AFSXR)}
Delay time, ACLKR/X transmit edge to AFSX/R output valid ACLKR/X int
-0.5
ACLKR/X ext in 1.9
ACLKR/X ext out
14
t_d(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output valid
ACLKR/X int
-1.4
ACLKR/X ext in 1.1
ACLKR/X ext out
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns.
(3) R = ACLKR/X period in ns.
MAX
6
24.5
7.1
24.2
UNIT
ns
ns
ns
ns
268 Timing Requirements and Switching Characteristics
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