DRA722_17 Datasheet, PDF (156/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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Table 5-11. Dual Voltage LVCMOS I2C DC Electrical Characteristics (continued)
PARAMETER
MIN
NOM
MAX
UNIT
t_OF
Output fall time from V_IHmin to V_ILmax with a bus
capacitance CB from 5 pF to 400 pF
I²C Fast Mode – 3.3 V
250
ns
V_IH
Input high-level threshold
0.7*VDDS
V_IL
Input low-level threshold
V_hys
Hysteresis
0.05*VDDS
I_IN
Input current at each I/O pin with an input voltage
31
between 0.1*VDDS to 0.9*VDDSS
V
0.3*VDDS
V
V
80
µA
I_OZ
I_OZ(I_PAD Current) for BIDI cell. This current is
31
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I_(PAD))
is measured and is reported as I_OZ
C_IN
Input capacitance
V_OL3
Output low-level threshold open-drain at 3-mA
sink current
80
µA
10
pF
0.4
V
I_OLmin
Low-level output current @V_OL=0.4V
3
mA
I_OLmin
Low-level output current @V_OL=0.6V for full drive
6
mA
load (400pF/400KHz)
t_OF
Output fall time from V_IHmin to V_ILmax with a bus
capacitance CB from 10 pF to 200 pF (Proper
External Resistor Value should be used as per
I2C spec)
20+0.1*Cb
250
ns
Output fall time from V_IHmin to V_ILmax with a bus
40
290
capacitance CB from 300 pF to 400 pF (Proper
External Resistor Value should be used as per
I2C spec)
(1) VDDS in this table stands for corresponding power supply (i.e. vddshv3). For more information on the power supply name and the
corresponding ball, see Table 4-2, POWER [10] column.
5.7.4 IQ1833 Buffers DC Electrical Characteristics
Table 5-12 summarizes the DC electrical characteristics for IQ1833 Buffers.
Table 5-12. IQ1833 Buffers DC Electrical Characteristics
PARAMETER
Signal Names in MUXMODE 0: tclk;
Balls: E20;
1.8-V Mode
V_IH
Input high-level threshold (Does not meet JEDEC V_IH)
V_IL
Input low-level threshold (Does not meet JEDEC V_IL)
MIN
NOM
0.75 *
VDDS
V_HYS
Input hysteresis voltage
100
I_IN
Input current at each I/O pin
2
C_PAD
Pad capacitance (including package capacitance)
3.3-V Mode
V_IH
V_IL
V_HYS
I_IN
C_PAD
Input high-level threshold (Does not meet JEDEC V_IH)
2.0
Input low-level threshold (Does not meet JEDEC V_IL)
Input hysteresis voltage
400
Input current at each I/O pin
5
Pad capacitance (including package capacitance)
MAX UNIT
V
0.25 *
V
VDDS
mV
11
µA
1
pF
V
0.6
V
mV
11
µA
1
pF
156 Specifications
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