DRA722_17 Datasheet, PDF (186/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 6-13. DPLL Type A Characteristics (continued)
NAME
DESCRIPTION
MIN
TYP
MAX
f_CLKOUTx2
CLKOUTx2 output frequency
40⁽¹⁾
20⁽³⁾
f_CLKOUTHIF
CLKOUTHIF output frequency
40⁽³⁾
2200⁽²⁾
1400⁽⁴⁾
2200⁽⁴⁾
f_CLKDCOLDO
DCOCLKLDO output
frequency
40
2800
t_lock
Frequency lock time
6 + 350 ×
REFCLK
p_lock
Phase lock time
6 + 500 ×
REFCLK
t_relock-L
p_relock-L
Relock time—Frequency
lock⁽⁵⁾ (LP relock time from
bypass)
Relock time—Phase lock⁽⁵⁾
(LP relock time from bypass)
6 + 70 ×
REFCLK
6 + 120 ×
REFCLK
t_relock-F
p_relock-F
Relock time—Frequency
lock⁽⁵⁾ (fast relock time from
bypass)
Relock time—Phase lock⁽⁵⁾
(fast relock time from bypass)
3.55 + 70 ×
REFCLK
3.55 + 120 ×
REFCLK
(1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
UNIT
MHz
MHz
MHz
MHz
µs
µs
µs
µs
µs
µs
COMMENTS
2 × [M / (N + 1)] × F_INP × [1 /
M2] (in locked condition)
F_INPHIF / M3 if clkinphifsel = 1
2 × [M / (N + 1)] × F_INP × [1 /
M3] if clkinphifsel = 0
2 × [M / (N + 1)] × F_INP (in
locked condition)
DPLL in LP relock time:
lowcurrstdby = 1
DPLL in LP relock time:
lowcurrstdby = 1
DPLL in fast relock time:
lowcurrstdby = 0
DPLL in fast relock time:
lowcurrstdby = 0
For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.
(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down
by factor of M3.
(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.
(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(6) Bypass mode: f_CLKOUT = F_INP if ulowclken = 0. For more information, see the Device TRM.
Table 6-14. DPLL Type B Characteristics
NAME
f_input
f_internal
f_CLKINPULOW
f_CLKLDOOUT
f_CLKOUT
f_CLKDCOLDO
t_J
t_lock
DESCRIPTION
CLKINP input clock frequency
REFCLK internal reference
clock frequency
CLKINPULOW bypass input
clock frequency
CLKOUTLDO output clock
frequency
CLKOUT output clock
frequency
Internal oscillator (DCO) output
clock frequency
CLKOUTLDO period jitter
CLKOUT period jitter
CLKDCOLDO period jitter
Frequency lock time
p_lock
t_relock-L
Phase lock time
Relock time—Frequency lock⁽³⁾
(LP relock time from bypass)
MIN
0.62
0.62
0.001
20⁽¹⁾⁽⁵⁾
20⁽¹⁾⁽⁵⁾
750⁽⁵⁾
1250⁽⁵⁾
–2.5%
TYP
MAX
60
2.5
600
2500⁽²⁾⁽⁵⁾
1450⁽²⁾⁽⁵⁾
1500⁽⁵⁾
2500⁽⁵⁾
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
COMMENTS
F_INP
[1 / (N + 1)] × F_INP
Bypass mode: f_CLKOUT =
f_CLKINPULOW / (M1 + 1) If
ulowclken = 1⁽⁴⁾
M / (N + 1)] × F_INP × [1 / M2]
(in locked condition)
[M / (N + 1)] × F_INP × [1 / M2]
(in locked condition)
[M / (N + 1)] × F_INP (in locked
condition)
2.5%
The period jitter at the output
clocks is ± 2.5% peak to peak
350 ×
REFCLKs
µs
500 ×
REFCLKs
µs
9 + 30 ×
REFCLKs
µs
186 Clock Specifications
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