DRA722_17 Datasheet, PDF (303/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
HSSD1
HSSD2H
HSSD2L
HSSD5
HSSD5
HSSD6
HSSD6
Figure 7-66. MMC/SD/SDIO in - High Speed - Transmitter Mode
SPRS906_TIMING_MMC1_04
7.25.1.3 SDR12, 4-bit data, half-cycle
Table 7-100 and Table 7-101 present Timing requirements and Switching characteristics for MMC1 -
SDR12 in receiver and transmitter mode (see Figure 7-67 and Figure 7-68).
Table 7-100. Timing Requirements for MMC1 - SD Card SDR12 Mode
NO. PARAMETER
SDR12 t_{su(cmdV-clkH)}
5
SDR12 t_h(clkH-cmdV)
6
SDR12 t_su(dV-clkH)
7
SDR12 t_h(clkH-dV)
8
DESCRIPTION
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
MODE
MIN
25.99
Pad Loopback Clock
Internal Loopback Clock
1.6
1.6
25.99
Pad Loopback Clock
1.6
Internal Loopback Clock 1.6
MAX UNIT
ns
ns
ns
ns
ns
ns
Table 7-101. Switching Characteristics for MMC1 - SD Card SDR12 Mode
NO. PARAMETER
SDR120 fop(clk)
SDR121 t_w(clkH)
DESCRIPTION
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
SDR122 t_w(clkL)
Pulse duration, mmc1_clk low
SDR123 t_d(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
SDR124 t_d(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
(1) P = output mmc1_clk period in ns
MIN
0.5*P-
0.185 ⁽¹⁾
0.5*P-
0.185⁽¹⁾
-19.13
-19.13
MAX
24
16.93
16.93
UNIT
MHz
ns
ns
ns
ns
SDR122
SDR121
SDR120
mmc1_clk
SDR126
SDR125
mmc1_cmd
mmc1_dat[3:0]
SDR128
SDR127
SPRS906_TIMING_MMC1_05
Figure 7-67. MMC/SD/SDIO in - High Speed SDR12 - Receiver Mode
Copyright © 2016–2017, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 303
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