DRA722_17 Datasheet, PDF (301/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
• Default speed, 4-bit data, SDR, half-cycle
• High speed, 4-bit data, SDR, half-cycle
• SDR12, 4-bit data, half-cycle
• SDR25, 4-bit data, half-cycle
• UHS-I SDR50, 4-bit data, half-cycle
• UHS-I SDR104, 4-bit data, half-cycle
• UHS-I DDR50, 4-bit data
NOTE
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
7.25.1.1 Default speed, 4-bit data, SDR, half-cycle
Table 7-96 and Table 7-97 present Timing requirements and Switching characteristics for MMC1 - Default
Speed in receiver and transmitter mode (see Figure 7-63 and Figure 7-64).
Table 7-96. Timing Requirements for MMC1 - SD Card Default Speed Mode
NO.
DSSD5
DSSD6
DSSD7
DSSD8
PARAMETER
t_{su(cmdV-clkH)}
t_h(clkH-cmdV)
t_su(dV-clkH)
t_h(clkH-dV)
DESCRIPTION
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
MIN
5.11
20.46
5.11
20.46
MAX
UNIT
ns
ns
ns
ns
Table 7-97. Switching Characteristics for MMC1 - SD Card Default Speed Mode
NO.
DSSD0
DSSD1
PARAMETER
fop(clk)
t_w(clkH)
DESCRIPTION
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
DSSD2 t_w(clkL)
Pulse duration, mmc1_clk low
DSSD3 t_d(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
DSSD4 t_d(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
(1) P = output mmc1_clk period in ns
MIN
0.5*P-
0.185 ⁽¹⁾
0.5*P-
0.185 ⁽¹⁾
-14.93
-14.93
MAX
24
14.93
14.93
UNIT
MHz
ns
ns
ns
ns
DSSD2
DSSD1
DSSD0
mmc1_clk
DSSD6
mmc1_cmd
mmc1_dat[3:0]
DSSD5
DSSD8
DSSD7
SPRS906_TIMING_MMC1_01
Figure 7-63. MMC/SD/SDIO in - Default Speed - Receiver Mode
Copyright © 2016–2017, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 301
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