DRA722_17 Datasheet, PDF (305/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
SDR251
SDR252H
SDR252L
HSSDR255
SDR255
SDR256
SDR256
SPRS906_TIMING_MMC1_08
Figure 7-70. MMC/SD/SDIO in - High Speed SDR25 - Transmitter Mode
7.25.1.5 UHS-I SDR50, 4-bit data, half-cycle
Table 7-104 and Table 7-105 present Timing requirements and Switching characteristics for MMC1 -
SDR50 in receiver and transmitter mode (see Figure 7-71 and Figure 7-72).
Table 7-104. Timing Requirements for MMC1 - SD Card SDR50 Mode
NO. PARAMETER
SDR50 t_{su(cmdV-clkH)}
3
SDR50 t_h(clkH-cmdV)
4
SDR50 t_su(dV-clkH)
7
SDR50 t_h(clkH-dV)
8
DESCRIPTION
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
MODE
Pad Loopback Clock
Internal Loopback Clock
MIN
1.48
1.7
1.48
1.7
1.6
MAX UNIT
ns
ns
ns
ns
ns
Table 7-105. Switching Characteristics for MMC1 - SD Card SDR50 Mode
NO. PARAMETER
SDR501 fop(clk)
SDR502 t_w(clkH)
H
SDR502L t_w(clkL)
DESCRIPTION
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
Pulse duration, mmc1_clk low
SDR505 t_d(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
SDR506 t_d(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
(1) P = output mmc1_clk period in ns
MIN
0.5*P-
0.185 ⁽¹⁾
0.5*P-
0.185 ⁽¹⁾
-8.8
-3.66
MAX
96
6.6
1.46
UNIT
MHz
ns
ns
ns
ns
SDR501
SDR502L
SDR502H
mmc1_clk
SDR503
SDR504
mmc1_cmd
SDR507
SDR508
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_09
Figure 7-71. MMC/SD/SDIO in - High Speed SDR50 - Receiver Mode
Copyright © 2016–2017, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 305
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