DRA722_17 Datasheet, PDF (133/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Table 5-7. Voltage Domains Operating Performance Points ⁽¹⁾ (continued)
DOMAIN
CONDITION
OPP_NOM
MIN ⁽³⁾ NOM ⁽²⁾ MAX ⁽³⁾
OPP_OD
MIN ⁽³⁾ NOM ⁽²⁾ MAX ⁽³⁾
MIN ⁽³⁾
OPP_HIGH
NOM ⁽²⁾ MAX DC MAX ⁽³⁾
(4)
Others (V)
BOOT (Before AVS is 1.02
enabled) ⁽⁵⁾
1.06
1.16
Not Applicable
Not Applicable
After AVS is enabled
(5)
AVS
Voltage
(6) _–
3.5%
AVS
Voltage
(6)
1.16
AVS
Voltage
(6) _–
3.5%
AVS
Voltage
(6)
AVS
Voltage
(6) _{+ 5%}
AVS
Voltage
(6) _–
3.5%
AVS
Voltage
(6)
AVS
Voltage
(6) _+2%
AVS
Voltage
(6) _{+ 5%}
(1) The voltage ranges in this table are preliminary, and final voltage ranges may be different than shown. Systems should be designed with
the ability to modify the voltage to comply with future recommendations.
(2) In a typical implementation, the power supply should target the NOM voltage.
(3) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(4) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(5) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.
(6) The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the
STD_FUSE_OPP Registers. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the
TRM. The power supply should be adjustable over the following ranges for each required OPP:
– OPP_NOM for MPU: 0.85 V – 1.15 V
– OPP_NOM for CORE and Others: 0.85 V - 1.15 V
– OPP_OD: 0.94 V - 1.15 V
– OPP_HIGH: 1.05 V - 1.25 V
The AVS voltages will be within the above specified ranges.
(7) VD_RTC can optionally be tied to VD_CORE and operate at the VD_CORE AVS voltages.
(8) The power supply must be programmed with the AVS voltages for the MPU and the CORE voltage domain, either just after the ROM
boot or at the earliest possible time in the secondary boot loader before there is significant activity seen on these domains.
Table 5-8 describes the standard processor clocks speed characteristics vs OPP of the device.
Table 5-8. Supported OPP vs Max Frequency ⁽²⁾
DESCRIPTION
VD_MPU
MPU_CLK
VD_DSP
DSP_CLK
VD_IVA
IVA_GCLK
VD_GPU
GPU_CLK
VD_CORE
CORE_IPUx_CLK
L3_CLK
DDR3 / DDR3L
VD_RTC
RTC_FCLK
OPP_NOM
Max Freq. (MHz)
1000
600
388.3
425.6
212.8
266
667 (DDR3-1333)
0.034
OPP_OD
Max Freq. (MHz)
1176
700
430
500
N/A
N/A
N/A
N/A
OPP_HIGH
Max Freq. (MHz)
1500
700
532
532
N/A
N/A
N/A
N/A
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Specifications 133