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DRA722_17 Datasheet, PDF (108/408 Pages) Texas Instruments – Infotainment Applications Processor
DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
4.4.18 Ethernet Interface (GMAC_SW)
CAUTION
The I/O timings provided in Section 7, Timing Requirements and Switching
Characteristics are valid only if signals within a single IOSET are used. The
IOSETs are defined in Table 7-72, Table 7-75, Table 7-80 and Table 7-87.
NOTE
For more information, see the Serial Communication Interfaces / Ethernet Controller section
of the device TRM.
SIGNAL NAME
rgmii0_txc
rgmii0_txctl
rgmii0_txd3
rgmii0_txd2
rgmii0_txd1
rgmii0_txd0
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd3
rgmii0_rxd2
rgmii0_rxd1
rgmii0_rxd0
rgmii1_txc
rgmii1_txctl
rgmii1_txd3
rgmii1_txd2
rgmii1_txd1
rgmii1_txd0
rgmii1_rxc
rgmii1_rxctl
rgmii1_rxd3
rgmii1_rxd2
rgmii1_rxd1
rgmii1_rxd0
mii1_rxd1
mii1_rxd2
mii1_rxd3
mii1_rxd0
mii1_rxclk
mii1_rxdv
mii1_txclk
mii1_txd0
mii1_txd1
mii1_txd2
Table 4-21. GMAC Signal Descriptions
DESCRIPTION
RGMII0 Transmit Clock
RGMII0 Transmit Enable
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII0 Receive Clock
RGMII0 Receive Control
RGMII0 Receive Data
RGMII0 Receive Data
RGMII0 Receive Data
RGMII0 Receive Data
RGMII1 Transmit Clock
RGMII1 Transmit Enable
RGMII1 Transmit Data
RGMII1 Transmit Data
RGMII1 Transmit Data
RGMII1 Transmit Data
RGMII1 Receive Clock
RGMII1 Receive Control
RGMII1 Receive Data
RGMII1 Receive Data
RGMII1 Receive Data
RGMII1 Receive Data
MII1 Receive Data
MII1 Receive Data
MII1 Receive Data
MII1 Receive Data
MII1 Receive Clock
MII1 Receive Data Valid
MII1 Transmit Clock
MII1 Transmit Data
MII1 Transmit Data
MII1 Transmit Data
TYPE
O
O
O
O
O
O
I
I
I
I
I
I
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
BALL
W9
V9
V7
U7
V6
U6
U5
V5
V4
V3
Y2
W2
D5
C2
C3
C4
B2
D6
C5
A3
B3
B4
B5
A4
C1
E4
F5
E6
D5
C2
C3
C4
B2
D6
108 Terminal Configuration and Functions
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