DRA722_17 Datasheet, PDF (189/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
SYMBOL
AE
FE
LE
Z
Table 7-1. Timing Parameters (continued)
SUBSCRIPTS
PARAMETER
Active Edge
First Edge
Last Edge
High impedance
7.3.1 Parameter Information
Tester Pin Electronics
Data Sheet Timing Reference Point
42 Ω
4.0 pF
3.5 nH
1.85 pF
Transmission Line
Z0 = 50 Ω
(see Note)
Output
Under
Test
Device Pin
(see Note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 7-1. Test Load Circuit for AC Timing Measurements
pm_tstcirc_prs403
The load capacitance value stated is only for characterization and measurement of AC timing signals.
This load capacitance value does not indicate the maximum load the device is capable of driving.
7.3.1.1 1.8V and 3.3V Signal Transition Levels
All input and output timing parameters are referenced to V_ref for both "0" and "1" logic levels. Vref = (VDD
I/O)/2.
V_ref
pm_io_volt_prs403
Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to V_IL MAX and V_IH MIN for input clocks, V_OL
MAX and V_OH MIN for output clocks.
Copyright © 2016–2017, Texas Instruments Incorporated
Timing Requirements and Switching Characteristics 189
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