DRA722_17 Datasheet, PDF (284/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
Table 7-64. Switching Characteristics for ULPI SDR Slave Mode
NO.
US4
US9
PARAMETER
t_d(clkH-stpV)
t_d(clkL-doV)
DESCRIPTION
Delay time, usb_ulpi_clk rising edge high to output
usb_ulpi_stp valid
Delay time, usb_ulpi_clk rising edge high to output
usb_ulpi_d[7:0] valid
MIN
0.44
0.44
MAX
8.35
8.35
UNIT
ns
ns
usbk_ulpi_clk
usbk_ulpi_stp
usbk_ulpi_dir_&_nxt
usbk_ulpi_d[7:0]
US1
US2
US3
US4
US4
US7
Data_IN
US9
US8
US6
US5
US9
Data_OUT
Figure 7-51. HS USB3 ULPI -SDR-Slave Mode-12-pin Mode
SPRS906_TIMING_USB_01
In Table 7-65 are presented the specific groupings of signals (IOSET) for use with USB3 signals.
SIGNALS
usb3_ulpi_d7
usb3_ulpi_d6
usb3_ulpi_d5
usb3_ulpi_d4
usb3_ulpi_d3
usb3_ulpi_d2
usb3_ulpi_d1
usb3_ulpi_d0
usb3_ulpi_nxt
usb3_ulpi_dir
usb3_ulpi_stp
usb3_ulpi_clk
BALL
AC5
AB4
AD4
AC4
AC7
AC6
AC9
AC3
AC8
AD6
AB8
AB5
Table 7-65. USB3 IOSETs
IOSET2
MUX
4
4
4
4
4
4
4
4
4
4
4
4
BALL
W2
Y2
V3
V4
V5
U5
U6
V6
U7
V7
V9
W9
IOSET3
MUX
6
6
6
6
6
6
6
6
6
6
6
6
7.20 Serial Advanced Technology Attachment (SATA)
The SATA RX/TX PHY interface is compliant with the SATA standard v2.6 for a maximum data rate:
• Gen2i, Gen2m, Gen2x: 3Gbps.
• Gen1i, Gen1m, Gen1x: 1.5Gbps.
NOTE
For more information, see the SATA Controller section of the Device TRM.
7.21 Peripheral Component Interconnect Express (PCIe)
284 Timing Requirements and Switching Characteristics
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