DRA722_17 Datasheet, PDF (235/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
GPMC_FCLK
gpmc_clk
gpmc_csi
gpmc_a[27:1]
gpmc_ben0
gpmc_ben1
FA5
FA1
FA9
FA10
FA10
Address 0
FA0
Valid
FA0
Valid
FA16
FA9
FA10
FA10
FA5
FA1
Address 1
FA0
Valid
FA0
Valid
gpmc_advn_ale
gpmc_oen_ren
gpmc_ad[15:0]
FA3
FA12
FA4
FA13
FA3
FA12
FA4
FA13
Data Upper
gpmc_waitj
FA15
FA14
DIR
OUT
IN
FA14
OUT
FA15
IN
GPMC_08
Figure 7-14. GPMC / NOR Flash - Asynchronous Read - 32-bit Timing^(1)(2)(3)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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Timing Requirements and Switching Characteristics 235
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