DRA722_17 Datasheet, PDF (160/408 Pages) Texas Instruments – Infotainment Applications Processor

DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
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5.7.11 Dual Voltage SDIO1833 DC Electrical Characteristics
Table 5-18 summarizes the DC electrical characteristics for Dual Voltage SDIO1833 Buffers.
Table 5-18. Dual Voltage SDIO1833 DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in Mode 0: mmc1_clk, mmc1_cmd, mmc1_data[3:0]
Bottom Balls: W6 / Y6 / AA6 / Y4 / AA5 / Y3
1.8-V Mode
V_IH
Input high-level threshold
V_IL
Input low-level threshold
V_HYS
Input hysteresis voltage
I_IN
Input current at each I/O pin
I_OZ
I_OZ(I_PAD Current) for BIDI cell. This current is contributed by the
tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as I_OZ
I_{IN with}
pulldown
Input current at each I/O pin with weak pulldown enabled
measured when PAD = VDDS
enabled
I_{IN with}
pullup
Input current at each I/O pin with weak pullup enabled measured
when PAD = 0
enabled
C_PAD
Pad capacitance (including package capacitance)
V_OH
Output high-level threshold (I_OH = 2 mA)
V_OL
Output low-level threshold (I_OL = 2 mA)
3.3-V Mode
1.27
50 ⁽²⁾
50
60
1.4
V
0.58
V
mV
30
µA
30
µA
120
210
µA
120
200
µA
5
pF
V
0.45
V
V_IH
Input high-level threshold
0.625 ×
V
VDDS
V_IL
V_HYS
I_IN
I_OZ
I_{IN with}
pulldown
enabled
I_{IN with}
pullup
enabled
C_PAD
V_OH
V_OL
Input low-level threshold
Input hysteresis voltage
Input current at each I/O pin
I_OZ(I_PAD Current) for BIDI cell. This current is contributed by the
tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as I_OZ
Input current at each I/O pin with weak pulldown enabled
measured when PAD = VDDS
Input current at each I/O pin with weak pullup enabled measured
when PAD = 0
Pad capacitance (including package capacitance)
Output high-level threshold (I_OH = 2 mA)
Output low-level threshold (I_OL = 2 mA)
40 ⁽²⁾
40
10
0.75 × VDDS
0.25 × VDDS
V
mV
110
µA
110
µA
100
290
µA
100
290
µA
5
pF
V
0.125 ×
V
VDDS
(1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball,
see Table 4-2, POWER [10] column.
(2) Hysteresis is enabled/disabled with CTRL_CORE_CONTROL_HYST_1.SDCARD_HYST register.
5.7.12 Dual Voltage LVCMOS DC Electrical Characteristics
Table 5-19 summarizes the DC electrical characteristics for Dual Voltage LVCMOS Buffers.
160 Specifications
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