DRA722_17 Datasheet, PDF (199/408 Pages) Texas Instruments – Infotainment Applications Processor

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DRA722, DRA724, DRA725, DRA726
SPRS956B – MARCH 2016 – REVISED JANUARY 2017
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See Table 7-2 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See Manual Functions Mapping for VIP1 2A IOSET10 for a definition of the Manual modes.
Table 7-6 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL
E21
F20
F21
B14
G13
J11
E12
F13
C12
D12
J14
E15
B15
A15
D15
B16
B17
A17
A20
C18
G16
D17
A21
AA3
AB3
AA4
AB9
B26
BALL NAME
gpio6_14
gpio6_15
gpio6_16
mcasp1_aclkr
mcasp1_axr2
mcasp1_axr3
mcasp1_axr4
mcasp1_axr5
mcasp1_axr6
mcasp1_axr7
mcasp1_fsr
mcasp2_aclkr
mcasp2_axr0
mcasp2_axr1
mcasp2_axr4
mcasp2_axr5
mcasp2_axr6
mcasp2_axr7
mcasp2_fsr
mcasp4_aclkx
mcasp4_axr0
mcasp4_axr1
mcasp4_fsx
mcasp5_aclkx
mcasp5_axr0
mcasp5_axr1
mcasp5_fsx
xref_clk2
Table 7-6. Manual Functions Mapping for VIP1 2A IOSET10
VIP_MANUAL1
A_DELAY (ps)
G_DELAY (ps)
1400
240
1170
240
1470
0
2145
200
2740
900
2933
200
2901
240
2600
840
2718
240
2983
240
2203
240
2143
240
2543
240
2664
240
2792
240
2621
300
1903
100
2928
200
2291
200
1433
0
2500
0
2379
100
1500
1400
3740
1850
3800
2760
4099
2500
3740
2100
0
0
VIP_MANUAL2
A_DELAY (ps)
G_DELAY (ps)
1767
0
1522
0
1600
0
2509
0
2680
1180
2700
600
2660
700
2640
920
3081
0
2540
800
2566
0
2492
0
2905
0
2730
400
2750
400
2983
0
2086
0
2670
700
2654
0
1540
0
2560
0
2599
0
1900
1040
3900
1700
3800
2800
3900
2870
3860
2060
0
0
CFG REGISTER
CFG_GPIO6_14_IN
CFG_GPIO6_15_IN
CFG_GPIO6_16_IN
CFG_MCASP1_ACLKR_IN
CFG_MCASP1_AXR2_IN
CFG_MCASP1_AXR3_IN
CFG_MCASP1_AXR4_IN
CFG_MCASP1_AXR5_IN
CFG_MCASP1_AXR6_IN
CFG_MCASP1_AXR7_IN
CFG_MCASP1_FSR_IN
CFG_MCASP2_ACLKR_IN
CFG_MCASP2_AXR0_IN
CFG_MCASP2_AXR1_IN
CFG_MCASP2_AXR4_IN
CFG_MCASP2_AXR5_IN
CFG_MCASP2_AXR6_IN
CFG_MCASP2_AXR7_IN
CFG_MCASP2_FSR_IN
CFG_MCASP4_ACLKX_IN
CFG_MCASP4_AXR0_IN
CFG_MCASP4_AXR1_IN
CFG_MCASP4_FSX_IN
CFG_MCASP5_ACLKX_IN
CFG_MCASP5_AXR0_IN
CFG_MCASP5_AXR1_IN
CFG_MCASP5_FSX_IN
CFG_XREF_CLK2_IN
MUXMODE
8
vin2a_hsync0
vin2a_vsync0
vin2a_fld0
vin2a_d0
vin2a_d2
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d1
vin2a_d8
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d9
vin2a_d16
vin2a_d18
vin2a_d19
vin2a_d17
vin2a_d20
vin2a_d22
vin2a_d23
vin2a_d21
vin2a_clk0
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Timing Requirements and Switching Characteristics 199